Searched refs:Offset (Results 1 - 21 of 21) sorted by relevance

/drivers/staging/rtl8723au/core/
H A Drtw_efuse.c645 u16 Offset,
650 *Value = pEEPROM->efuse_eeprom_data[Offset];
657 u16 Offset,
662 *Value = pEEPROM->efuse_eeprom_data[Offset];
663 *Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8;
670 u16 Offset,
675 *Value = pEEPROM->efuse_eeprom_data[Offset];
676 *Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8;
677 *Value |= pEEPROM->efuse_eeprom_data[Offset+2]<<16;
678 *Value |= pEEPROM->efuse_eeprom_data[Offset
643 efuse_ShadowRead1Byte( struct rtw_adapter * pAdapter, u16 Offset, u8 *Value) argument
655 efuse_ShadowRead2Byte( struct rtw_adapter * pAdapter, u16 Offset, u16 *Value) argument
668 efuse_ShadowRead4Byte( struct rtw_adapter * pAdapter, u16 Offset, u32 *Value) argument
730 EFUSE_ShadowRead23a( struct rtw_adapter * pAdapter, u8 Type, u16 Offset, u32 *Value) argument
[all...]
/drivers/mtd/
H A Dftl.c116 uint32_t Offset; member in struct:partition_t::eun_info_t
122 uint32_t Offset; member in struct:partition_t::xfer_info_t
215 part->EUNInfo[i].Offset = 0xffffffff;
236 (part->EUNInfo[le16_to_cpu(header.LogicalEUN)].Offset == 0xffffffff)) {
237 part->EUNInfo[le16_to_cpu(header.LogicalEUN)].Offset = offset;
256 part->XferInfo[xtrans].Offset = offset;
289 offset = part->EUNInfo[i].Offset + le32_to_cpu(header.BAMOffset);
341 pr_debug("ftl_cs: erasing xfer unit at 0x%x\n", xfer->Offset);
353 erase->addr = xfer->Offset;
384 if (part->XferInfo[i].Offset
[all...]
/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phy.c51 u32 Offset);
54 u32 Offset, u32 Data);
111 enum rf90_radio_path eRFPath, u32 Offset)
118 Offset &= 0x3f;
122 if (Offset >= 31) {
127 NewOffset = Offset - 30;
128 } else if (Offset >= 16) {
135 NewOffset = Offset - 15;
137 NewOffset = Offset;
141 NewOffset = Offset;
110 rtl8192_phy_RFSerialRead(struct net_device *dev, enum rf90_radio_path eRFPath, u32 Offset) argument
167 rtl8192_phy_RFSerialWrite(struct net_device *dev, enum rf90_radio_path eRFPath, u32 Offset, u32 Data) argument
286 phy_FwRFSerialRead(struct net_device *dev, enum rf90_radio_path eRFPath, u32 Offset) argument
312 phy_FwRFSerialWrite(struct net_device *dev, enum rf90_radio_path eRFPath, u32 Offset, u32 Data) argument
1279 rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, enum ht_extchnl_offset Offset) argument
[all...]
H A Dr8192E_phy.h104 enum ht_extchnl_offset Offset);
H A Dr8190P_def.h307 u8 Offset; member in struct:tx_desc
H A Dr8192E_dev.c1234 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1308 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1310 entry_tmp->Offset);
/drivers/staging/rtl8723au/hal/
H A Drtl8723a_phycfg.c150 * u32 Offset, The target address to be read
164 u32 Offset)
175 Offset &= 0x3f;
180 NewOffset = Offset;
247 * u32 Offset, The target address to be read
285 u32 Offset, u32 Data)
300 Offset &= 0x3f;
305 /* PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */
310 NewOffset = Offset;
1061 enum ht_channel_width Bandwidth, unsigned char Offset)
163 phy_RFSerialRead(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, u32 Offset) argument
284 phy_RFSerialWrite(struct rtw_adapter *Adapter, enum RF_RADIO_PATH eRFPath, u32 Offset, u32 Data) argument
1060 PHY_SetBWMode23a8723A(struct rtw_adapter *Adapter, enum ht_channel_width Bandwidth, unsigned char Offset) argument
[all...]
/drivers/staging/rtl8723au/include/
H A DHal8723APhyCfg.h137 u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
198 unsigned char Offset);
H A Drtw_efuse.h107 void EFUSE_ShadowRead23a(struct rtw_adapter *pAdapter, u8 Type, u16 Offset, u32 *Value);
/drivers/staging/rtl8192e/
H A Drtl819x_HTProc.c686 enum ht_extchnl_offset Offset);
1040 enum ht_extchnl_offset Offset)
1056 Offset == HT_EXTCHNL_OFFSET_LOWER)
1057 Offset = HT_EXTCHNL_OFFSET_NO_EXT;
1058 if (Offset == HT_EXTCHNL_OFFSET_UPPER ||
1059 Offset == HT_EXTCHNL_OFFSET_LOWER) {
1061 pHTInfo->CurSTAExtChnlOffset = Offset;
1038 HTSetConnectBwMode(struct rtllib_device *ieee, enum ht_channel_width Bandwidth, enum ht_extchnl_offset Offset) argument
H A Drtllib.h2490 enum ht_extchnl_offset Offset);
2892 enum ht_extchnl_offset Offset);
/drivers/staging/rtl8192u/ieee80211/
H A Drtl819x_HTProc.c942 void HTSetConnectBwMode(struct ieee80211_device *ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
1347 void HTSetConnectBwMode(struct ieee80211_device *ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) argument
1359 // (pHTInfo->bCurBW40MHz==true && Bandwidth==HT_CHANNEL_WIDTH_20_40 && Offset==pHTInfo->CurSTAExtChnlOffset))
1371 if(ieee->current_network.channel<2 && Offset==HT_EXTCHNL_OFFSET_LOWER)
1372 Offset = HT_EXTCHNL_OFFSET_NO_EXT;
1373 if(Offset==HT_EXTCHNL_OFFSET_UPPER || Offset==HT_EXTCHNL_OFFSET_LOWER) {
1375 pHTInfo->CurSTAExtChnlOffset = Offset;
H A Dieee80211.h2186 void (*SetBWModeHandler)(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
2533 void HTSetConnectBwMode(struct ieee80211_device *ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
/drivers/staging/rtl8188eu/include/
H A Dhal_intf.h180 u8 Offset);
310 enum ht_channel_width Bandwidth, u8 Offset);
/drivers/video/fbdev/riva/
H A Driva_hw.c1881 NV_WR32(&Surface->Offset, 0, surf0);
1883 NV_WR32(&Surface->Offset, 0, surf1);
1897 NV_WR32(&Surface->Offset, 0, surf0);
1899 NV_WR32(&Surface->Offset, 0, surf1);
1913 NV_WR32(&Surface->Offset, 0, surf0);
1915 NV_WR32(&Surface->Offset, 0, surf1);
1930 NV_WR32(&Surface->Offset, 0, surf0);
1932 NV_WR32(&Surface->Offset, 0, surf1);
1946 NV_WR32(&Surface->Offset, 0, surf0);
1948 NV_WR32(&Surface->Offset,
[all...]
H A Driva_hw.h390 U032 Offset; member in struct:__anon7230
/drivers/net/ethernet/atheros/atlx/
H A Datl2.h92 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue);
165 * (Offset 0x1400). */
H A Datl2.c2764 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) argument
2769 if (Offset & 0x3)
2773 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
/drivers/staging/rtl8192u/
H A Dr8192U.h217 u8 Offset; member in struct:_tx_desc_819x_usb
256 u8 Offset; member in struct:_tx_desc_819x_usb_aggr_subframe
367 u8 Offset; member in struct:_rx_desc_819x_usb_aggr_subframe
679 /* Bandwidth Offset */
733 /* Tx IQ DC Offset and Tx DFIR type:
H A Dr8192U_core.c1570 tx_desc->Offset = sizeof(tx_fwinfo_819x_usb) + 8;
/drivers/message/fusion/
H A Dmptbase.h227 u8 Offset; /* 00h */ member in struct:_ATTO_DEVICE_INFO

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