Searched refs:REG_GET (Results 1 - 9 of 9) sorted by relevance

/drivers/video/fbdev/omap2/dss/
H A Dhdmi.h285 #define REG_GET(base, idx, start, end) \ macro
292 while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
H A Dhdmi4_core.c57 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
129 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
134 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
143 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
150 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
158 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
H A Dhdmi_wp.c72 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
H A Ddsi.c120 #define REG_GET(dsidev, idx, start, end) \ macro
506 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
513 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
2059 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2555 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2566 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2589 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2616 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2635 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2790 while (REG_GET(dside
[all...]
H A Ddss.c60 #define REG_GET(idx, start, end) \ macro
564 return REG_GET(DSS_CONTROL, 15, 15);
H A Ddispc.c55 #define REG_GET(idx, start, end) \ macro
252 return REG_GET(rfld.reg, rfld.high, rfld.low);
563 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
571 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
576 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
1129 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1195 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1197 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
2659 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
3456 cinfo->lck_div = REG_GET(DISPC_DIVISOR
[all...]
H A Dhdmi5_core.c173 stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
193 pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
H A Dhdmi5.c345 idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
/drivers/gpu/drm/radeon/
H A Dradeon.h2485 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) macro

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