Searched refs:RF_CHNLBW (Results 1 - 25 of 46) sorted by relevance

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/drivers/net/wireless/rtlwifi/rtl8192ee/
H A Drf.c44 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
46 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
52 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
54 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
H A Dhw.c1235 RF_CHNLBW, RFREG_OFFSET_MASK);
1237 RF_CHNLBW, RFREG_OFFSET_MASK);
1243 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
1245 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
/drivers/net/wireless/rtlwifi/rtl8821ae/
H A Drf.c41 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 3);
42 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 3);
45 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 1);
46 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 1);
49 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 0);
50 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 0);
/drivers/staging/rtl8188eu/hal/
H A Drf.c35 phy_set_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,
41 phy_set_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,
H A Dphy.c350 param1 = RF_CHNLBW;
1387 lc_cal = phy_query_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits);
1390 phy_set_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits,
/drivers/net/wireless/rtlwifi/rtl8188ee/
H A Drf.c44 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
50 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
/drivers/net/wireless/rtlwifi/rtl8192ce/
H A Drf.c48 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
54 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
H A Dhw.c999 RF_CHNLBW, RFREG_OFFSET_MASK);
1001 RF_CHNLBW, RFREG_OFFSET_MASK);
/drivers/net/wireless/rtlwifi/rtl8192cu/
H A Drf.c48 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
54 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
/drivers/net/wireless/rtlwifi/rtl8192se/
H A Drf.c521 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
527 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
H A Dreg.h1117 #define RF_CHNLBW 0x18 macro
/drivers/net/wireless/rtlwifi/rtl8723ae/
H A Drf.c44 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
50 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
/drivers/net/wireless/rtlwifi/rtl8723be/
H A Drf.c44 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
50 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
/drivers/staging/rtl8723au/hal/
H A Drtl8723a_rf6052.c83 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
87 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
H A Drtl8723a_phycfg.c1086 param1 = RF_CHNLBW, param2 = channel */
1087 param1 = RF_CHNLBW;
H A DHalDMOutSrc8723A_CE.c914 LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
917 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
H A Dusb_halinit.c673 pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)0, RF_CHNLBW, bRFRegOffsetMask);
674 pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)1, RF_CHNLBW, bRFRegOffsetMask);
/drivers/net/wireless/rtlwifi/rtl8192de/
H A Drf.c49 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) |
62 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11),
H A Dphy.c2608 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2631 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2792 RF_CHNLBW, channel, 0);
3519 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3526 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3565 RF_CHNLBW, RFREG_OFFSET_MASK);
H A Dreg.h1236 #define RF_CHNLBW 0x18 macro
/drivers/staging/rtl8712/
H A Drtl871x_mp.c392 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
396 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
H A Drtl871x_mp_phy_regdef.h339 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ macro
/drivers/staging/rtl8188eu/include/
H A DHal8188EPhyReg.h405 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ macro
H A Drtw_mp_phy_regdef.h364 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ macro
/drivers/staging/rtl8723au/include/
H A DHal8723APhyReg.h360 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ macro

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