Searched refs:SMU_SCLK_DPM_STATE_0_CNTL_0 (Results 1 - 3 of 3) sorted by relevance

/drivers/gpu/drm/radeon/
H A Dtrinity_dpm.h28 #define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0)
H A Dtrinityd.h34 #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000 macro
H A Dtrinity_dpm.c594 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
597 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
641 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
644 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
646 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
649 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
737 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
741 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);

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