Searched refs:TXQ_CTRL_TXF_BURST_NUM_SHIFT (Results 1 - 3 of 3) sorted by relevance

/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_hw.h434 #define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */ macro
/drivers/net/ethernet/atheros/atlx/
H A Datl1.h157 #define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 macro
H A Datl1.c1583 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |

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