Searched refs:UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (Results 1 - 2 of 2) sorted by relevance
| /drivers/clk/tegra/ | ||
| H A D | clk-tegra114.c | 138 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) macro |
| H A D | clk-tegra124.c | 109 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) macro |
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