Searched refs:boxes (Results 1 - 11 of 11) sorted by relevance

/drivers/gpu/drm/savage/
H A Dsavage_state.c795 const struct drm_clip_rect *boxes)
824 x = boxes[i].x1, y = boxes[i].y1;
825 w = boxes[i].x2 - boxes[i].x1;
826 h = boxes[i].y2 - boxes[i].y1;
864 unsigned int nbox, const struct drm_clip_rect *boxes)
882 DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[
791 savage_dispatch_clear(drm_savage_private_t * dev_priv, const drm_savage_cmd_header_t * cmd_header, const drm_savage_cmd_header_t *data, unsigned int nbox, const struct drm_clip_rect *boxes) argument
863 savage_dispatch_swap(drm_savage_private_t * dev_priv, unsigned int nbox, const struct drm_clip_rect *boxes) argument
892 savage_dispatch_draw(drm_savage_private_t * dev_priv, const drm_savage_cmd_header_t *start, const drm_savage_cmd_header_t *end, const struct drm_buf * dmabuf, const unsigned int *vtxbuf, unsigned int vb_size, unsigned int vb_stride, unsigned int nbox, const struct drm_clip_rect *boxes) argument
[all...]
/drivers/gpu/drm/r128/
H A Dr128_state.c40 struct drm_clip_rect *boxes, int count)
50 OUT_RING(boxes[0].x1);
51 OUT_RING(boxes[0].x2 - 1);
52 OUT_RING(boxes[0].y1);
53 OUT_RING(boxes[0].y2 - 1);
59 OUT_RING(boxes[1].x1);
60 OUT_RING(boxes[1].x2 - 1);
61 OUT_RING(boxes[1].y1);
62 OUT_RING(boxes[1].y2 - 1);
68 OUT_RING(boxes[
39 r128_emit_clip_rects(drm_r128_private_t *dev_priv, struct drm_clip_rect *boxes, int count) argument
[all...]
/drivers/gpu/drm/radeon/
H A Dradeon_state.c774 x += master_priv->sarea_priv->boxes[0].x1;
775 y += master_priv->sarea_priv->boxes[0].y1;
824 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
828 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
833 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
838 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
846 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
851 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
884 struct drm_clip_rect *pbox = sarea_priv->boxes;
1256 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[
2785 struct drm_clip_rect __user *boxes = cmdbuf->boxes; local
[all...]
H A Dradeon_ioc32.c243 u32 boxes; member in struct:drm_radeon_cmd_buffer32
261 || __put_user((void __user *)(unsigned long)req32.boxes,
262 &request->boxes))
H A Dradeon_irq.c250 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
H A Dradeon_cp.c329 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
359 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
383 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1992 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
H A Dradeon_drv.h223 u32 boxes; member in struct:drm_radeon_private::__anon1031
334 struct drm_clip_rect __user *boxes; member in struct:drm_radeon_kcmd_buffer
472 /* Flags for stats.boxes
2001 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
2004 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
H A Dr600_cp.c106 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
131 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2424 struct drm_clip_rect *pbox = sarea_priv->boxes;
H A Dr300_cmdbuf.c79 (&box, &cmdbuf->boxes[n + i], sizeof(box))) {
/drivers/gpu/drm/mga/
H A Dmga_state.c487 struct drm_clip_rect *pbox = sarea_priv->boxes;
575 struct drm_clip_rect *pbox = sarea_priv->boxes;
643 &sarea_priv->boxes[i]);
690 &sarea_priv->boxes[i]);
773 struct drm_clip_rect *pbox = sarea_priv->boxes;
/drivers/gpu/drm/i810/
H A Di810_dma.c594 struct drm_clip_rect *pbox = sarea_priv->boxes;
667 struct drm_clip_rect *pbox = sarea_priv->boxes;
714 struct drm_clip_rect *box = sarea_priv->boxes;

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