Searched refs:chid (Results 1 - 25 of 57) sorted by relevance

123

/drivers/usb/wusbcore/
H A Dwusbhc.c97 const struct wusb_ckhdid *chid; local
101 chid = &wusbhc->wuie_host_info->CHID;
103 chid = &wusb_ckhdid_zero;
105 result += ckhdid_printf(buf, PAGE_SIZE, chid);
124 struct wusb_ckhdid chid; local
132 &chid.data[0] , &chid.data[1] ,
133 &chid.data[2] , &chid.data[3] ,
134 &chid
[all...]
H A Dmmc.c267 int wusbhc_chid_set(struct wusbhc *wusbhc, const struct wusb_ckhdid *chid) argument
271 if (memcmp(chid, &wusb_ckhdid_zero, sizeof(*chid)) == 0)
272 chid = NULL;
275 if (chid) {
280 wusbhc->chid = *chid;
285 if ((chid) && (wusbhc->uwb_rc == NULL)) {
302 if (chid)
H A Dcbaf.c110 struct wusb_ckhdid chid; member in struct:cbaf
256 hi->CHID = cbaf->chid;
321 ckhdid_printf(pr_chid, sizeof(pr_chid), &cbaf->chid);
338 &cbaf->chid.data[0] , &cbaf->chid.data[1],
339 &cbaf->chid.data[2] , &cbaf->chid.data[3],
340 &cbaf->chid.data[4] , &cbaf->chid.data[5],
341 &cbaf->chid
[all...]
/drivers/gpu/drm/nouveau/core/engine/fifo/
H A Dbase.c95 for (chan->chid = priv->min; chan->chid < priv->max; chan->chid++) {
96 if (!priv->channel[chan->chid]) {
97 priv->channel[chan->chid] = nv_object(chan);
103 if (chan->chid == priv->max) {
109 addr + size * chan->chid;
125 priv->channel[chan->chid] = NULL;
225 return nouveau_fifo_chan(object)->chid;
233 nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid) argument
[all...]
H A Dnv04.c66 u32 context, chid = chan->base.chid; local
90 context |= chid << 24;
93 ret = nouveau_ramht_insert(priv->ramht, chid, handle, context);
111 nv_engctx(object)->addr = nouveau_fifo_chan(parent)->chid;
145 args->v0.chid = chan->base.chid;
150 chan->ramfc = chan->base.chid * 32;
184 u32 mask = 1 << chan->base.chid;
207 u32 chid; local
363 nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) argument
415 nv04_fifo_cache_error(struct nouveau_device *device, struct nv04_fifo_priv *priv, u32 chid, u32 get) argument
461 nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv, u32 chid) argument
516 uint32_t chid, get; local
[all...]
H A Dnvc0.c171 nv_wr32(priv, 0x002634, chan->base.chid);
172 if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
174 chan->base.chid, nouveau_client_name(chan));
224 args->v0.chid = chan->base.chid;
229 usermem = chan->base.chid * 0x1000;
262 u32 chid = chan->base.chid; local
269 nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
272 nv_wr32(priv, 0x003004 + (chid *
286 u32 chid = chan->base.chid; local
449 u32 chid = chan->base.chid; local
465 nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) argument
509 u32 chid = (stat & 0x0000007f); local
694 u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f; local
[all...]
H A Dnv40.c76 u32 context, chid = chan->base.chid; local
99 context |= chid << 23;
102 ret = nouveau_ramht_insert(priv->ramht, chid, handle, context);
135 if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)
171 if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)
211 args->v0.chid = chan->base.chid;
217 chan->ramfc = chan->base.chid * 128;
H A Dnve0.c197 nv_wr32(priv, 0x002634, chan->base.chid);
198 if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
200 chan->base.chid, nouveau_client_name(chan));
261 args->v0.chid = chan->base.chid;
267 usermem = chan->base.chid * 0x200;
284 nv_wo32(base, 0xe8, chan->base.chid);
298 u32 chid = chan->base.chid; local
305 nv_mask(priv, 0x800004 + (chid *
322 u32 chid = chan->base.chid; local
475 u32 chid = chan->base.chid; local
491 nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) argument
563 u32 chid = load ? next : prev; local
835 u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff; local
[all...]
H A Dnv10.c87 args->v0.chid = chan->base.chid;
92 chan->ramfc = chan->base.chid * 32;
H A Dnv50.c142 chan->base.chid, nouveau_client_name(chan));
224 args->v0.chid = chan->base.chid;
288 args->v0.chid = chan->base.chid;
333 u32 chid = chan->base.chid; local
340 nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12);
350 u32 chid = chan->base.chid; local
[all...]
/drivers/gpu/drm/nouveau/core/core/
H A Dramht.c29 nouveau_ramht_hash(struct nouveau_ramht *ramht, int chid, u32 handle) argument
38 hash ^= chid << (ramht->bits - 4);
44 nouveau_ramht_insert(struct nouveau_ramht *ramht, int chid, argument
50 co = ho = nouveau_ramht_hash(ramht, chid, handle);
/drivers/gpu/drm/nouveau/core/engine/graph/
H A Dnv20.h16 int chid; member in struct:nv20_graph_chan
H A Dnv20.c60 chan->chid = nouveau_fifo_chan(parent)->chid;
62 nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
120 nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
129 int chid = -1; local
133 chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
134 if (chan->chid == chid) {
143 nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
206 u32 chid local
[all...]
H A Dnv2a.c32 chan->chid = nouveau_fifo_chan(parent)->chid;
34 nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
H A Dnv10.c400 int chid; member in struct:nv10_graph_chan
613 int chid = nv_rd32(priv, 0x400148) >> 24; local
614 if (chid < ARRAY_SIZE(priv->chan))
615 chan = priv->chan[chid];
868 nv10_graph_load_dma_vtxbuf(struct nv10_graph_chan *chan, int chid, u32 inst) argument
916 0x2c000000 | chid << 20 | subchan << 16 | 0x18c);
938 nv10_graph_load_context(struct nv10_graph_chan *chan, int chid) argument
956 nv10_graph_load_dma_vtxbuf(chan, chid, inst);
959 nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24);
992 int chid; local
1166 u32 chid = (addr & 0x01f00000) >> 20; local
[all...]
H A Dnv04.c362 int chid; member in struct:nv04_graph_chan
1045 int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24; local
1046 if (chid < ARRAY_SIZE(priv->chan))
1047 chan = priv->chan[chid];
1053 nv04_graph_load_context(struct nv04_graph_chan *chan, int chid) argument
1062 nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24);
1087 int chid; local
1098 chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f;
1099 next = priv->chan[chid];
1101 nv04_graph_load_context(next, chid);
1266 u32 chid = (addr & 0x0f000000) >> 24; local
[all...]
/drivers/gpu/drm/nouveau/core/include/core/
H A Dramht.h11 int nouveau_ramht_insert(struct nouveau_ramht *, int chid,
/drivers/gpu/drm/nouveau/core/engine/disp/
H A Dnvd0.c81 u32 data = (chan->chid << 27) | (addr << 9) | 0x00000001;
82 return nouveau_ramht_insert(base->ramht, chan->chid, name, data);
97 int chid = dmac->base.chid; local
105 nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
108 nv_wr32(priv, 0x610494 + (chid * 0x0010), dmac->push);
109 nv_wr32(priv, 0x610498 + (chid * 0x0010), 0x00010000);
110 nv_wr32(priv, 0x61049c + (chid * 0x0010), 0x00000001);
111 nv_mask(priv, 0x610490 + (chid *
130 int chid = dmac->base.chid; local
545 int chid = pioc->base.chid; local
571 int chid = pioc->base.chid; local
1143 nvd0_disp_intr_error(struct nv50_disp_priv *priv, int chid) argument
1199 int chid = __ffs(stat); stat &= ~(1 << chid); local
1208 int chid = ffs(stat) - 1; local
[all...]
H A Dnv50.c58 int chid = impl->chid + head; local
61 if (base->chan & (1 << chid))
63 base->chan |= (1 << chid);
71 chan->chid = chid;
82 base->chan &= ~(1 << chan->chid);
101 nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid) argument
106 nvkm_event_send(&priv->uevent, 1, chid, &rep, sizeof(rep));
122 notify->index = dmac->base.chid;
188 u32 chid = chan->chid; local
256 int chid = dmac->base.chid; local
289 int chid = dmac->base.chid; local
802 int chid = pioc->base.chid; local
831 int chid = pioc->base.chid; local
1323 nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid) argument
1928 u32 chid = __ffs(intr0 & 0x001f0000) - 16; local
1934 u32 chid = __ffs(intr0 & 0x0000001f); local
[all...]
/drivers/gpu/drm/nouveau/core/engine/copy/
H A Dnva3.c96 int chid; local
99 chid = pfifo->chid(pfifo, engctx);
105 chid, inst << 12, nouveau_client_name(engctx), subc,
/drivers/gpu/drm/nouveau/core/engine/crypt/
H A Dnv84.c123 int chid; local
126 chid = pfifo->chid(pfifo, engctx);
132 chid, (u64)inst << 12, nouveau_client_name(engctx),
H A Dnv98.c97 int chid; local
100 chid = pfifo->chid(pfifo, engctx);
106 chid, (u64)inst << 12, nouveau_client_name(engctx),
/drivers/gpu/drm/nouveau/core/engine/mpeg/
H A Dnv44.c115 int chid; local
118 chid = pfifo->chid(pfifo, engctx);
141 chid, inst << 4, nouveau_client_name(engctx), stat,
/drivers/gpu/drm/nouveau/
H A Dnouveau_chan.h11 int chid; member in struct:nouveau_channel
/drivers/gpu/drm/nouveau/core/include/engine/
H A Dfifo.h16 u16 chid; member in struct:nouveau_fifo_chan
80 int (*chid)(struct nouveau_fifo *, struct nouveau_object *); member in struct:nouveau_fifo
103 nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid);

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