/drivers/media/tuners/ |
H A D | e4000.h | 38 * clock 40 u32 clock; member in struct:e4000_config
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H A D | m88ts2022.h | 24 * clock 27 u32 clock; member in struct:m88ts2022_config 35 * clock output 43 * clock output divider
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H A D | fc2580.h | 35 * clock 37 u32 clock; member in struct:fc2580_config
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/drivers/clk/shmobile/ |
H A D | clk-div6.c | 26 * struct div6_clock - CPG 6 bit divider clock 41 struct div6_clock *clock = to_div6_clock(hw); local 43 clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg); 50 struct div6_clock *clock = to_div6_clock(hw); local 53 * the clock. 56 clock->reg); 61 struct div6_clock *clock = to_div6_clock(hw); local 63 return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP); 69 struct div6_clock *clock local 95 struct div6_clock *clock = to_div6_clock(hw); local 119 struct div6_clock *clock; local [all...] |
H A D | clk-mstp.c | 22 * status register when enabling the clock. 43 * struct mstp_clock - MSTP gating clock 58 struct mstp_clock *clock = to_mstp_clock(hw); local 59 struct mstp_clock_group *group = clock->group; 60 u32 bitmask = BIT(clock->bit_index); 87 group->smstpcr, clock->bit_index); 106 struct mstp_clock *clock = to_mstp_clock(hw); local 107 struct mstp_clock_group *group = clock->group; 115 return !(value & BIT(clock->bit_index)); 129 struct mstp_clock *clock; local [all...] |
/drivers/gpu/drm/gma500/ |
H A D | gma_device.c | 21 uint32_t clock; local 29 pci_read_config_dword(pci_root, 0xD4, &clock); 32 switch (clock & 0x07) {
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H A D | oaktrail_crtc.c | 120 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ 121 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) argument 123 clock->dot = (refclk * clock->m) / (14 * clock->p1); 126 static void mrst_print_pll(struct gma_clock_t *clock) argument 129 clock->dot, clock->m, clock->m1, clock 137 struct gma_clock_t clock; local 194 struct gma_clock_t clock; local 376 struct gma_clock_t clock; local [all...] |
H A D | cdv_intel_display.c | 218 * DPLL reference clock is on in the DPLL control register, but before 223 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) 253 * refclka mean use clock from same PLL 255 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll 281 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); 297 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); 299 if (clock->vco < 2250000) { 302 } else if (clock->vco < 2750000) { 305 } else if (clock->vco < 3300000) { 321 p |= SET_FIELD(clock 222 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) argument 402 cdv_intel_clock(int refclk, struct gma_clock_t *clock) argument 416 struct gma_clock_t clock; local 590 struct gma_clock_t clock; local 840 i8xx_clock(int refclk, struct gma_clock_t *clock) argument 858 struct gma_clock_t clock; local [all...] |
H A D | psb_intel_display.c | 76 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) argument 78 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 79 clock->p = clock->p1 * clock->p2; 80 clock->vco = refclk * clock->m / (clock 114 struct gma_clock_t clock; local 316 struct gma_clock_t clock; local [all...] |
H A D | gma_display.h | 57 void (*clock)(int refclk, struct gma_clock_t *clock); member in struct:gma_clock_funcs 61 struct gma_clock_t *clock); 97 /* Common clock related functions */ 99 extern void gma_clock(int refclk, struct gma_clock_t *clock); 102 struct gma_clock_t *clock);
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H A D | gma_display.c | 701 struct gma_clock_t *clock) 703 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 705 if (clock->p < limit->p.min || limit->p.max < clock->p) 707 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 709 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 712 if (clock 699 gma_pll_is_valid(struct drm_crtc *crtc, const struct gma_limit_t *limit, struct gma_clock_t *clock) argument 737 struct gma_clock_t clock; local [all...] |
/drivers/video/fbdev/via/ |
H A D | via_clock.c | 23 * clock and PLL management functions 275 printk(KERN_INFO "Using undocumented set clock state.\n%s", via_slap); 280 printk(KERN_INFO "Using undocumented set clock source.\n%s", via_slap); 297 void via_clock_init(struct via_clock *clock, int gfx_chip) argument 302 clock->set_primary_clock_state = dummy_set_clock_state; 303 clock->set_primary_clock_source = dummy_set_clock_source; 304 clock->set_primary_pll_state = dummy_set_pll_state; 305 clock->set_primary_pll = cle266_set_primary_pll; 307 clock->set_secondary_clock_state = dummy_set_clock_state; 308 clock [all...] |
/drivers/clocksource/ |
H A D | clps711x-timer.c | 34 static int __init _clps711x_clksrc_init(struct clk *clock, void __iomem *base) argument 40 if (IS_ERR(clock)) 41 return PTR_ERR(clock); 43 rate = clk_get_rate(clock); 69 static int __init _clps711x_clkevt_init(struct clk *clock, void __iomem *base, argument 79 if (IS_ERR(clock)) 80 return PTR_ERR(clock); 86 rate = clk_get_rate(clock); 116 struct clk *clock = of_clk_get(np, 0); local 121 BUG_ON(_clps711x_clksrc_init(clock, bas [all...] |
/drivers/net/phy/ |
H A D | dp83640.c | 111 struct dp83640_clock *clock; member in struct:dp83640_private 136 /* we create one clock instance per MII bus */ 150 /* reference to our PTP hardware clock */ 177 "The address of the PHY to use for the ancillary clock features"); 233 if (dp83640->clock->page != page) { 235 dp83640->clock->page = page; 248 if (dp83640->clock->page != page) { 250 dp83640->clock->page = page; 305 static int periodic_output(struct dp83640_clock *clock, argument 309 struct dp83640_private *dp83640 = clock 378 struct dp83640_clock *clock = local 411 struct dp83640_clock *clock = local 432 struct dp83640_clock *clock = local 457 struct dp83640_clock *clock = local 474 struct dp83640_clock *clock = local 516 struct dp83640_clock *clock = local 604 recalibrate(struct dp83640_clock *clock) argument 962 struct dp83640_clock *clock; local 984 dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) argument 1015 choose_this_phy(struct dp83640_clock *clock, struct phy_device *phydev) argument 1027 dp83640_clock_get(struct dp83640_clock *clock) argument 1040 struct dp83640_clock *clock = NULL, *tmp; local 1074 dp83640_clock_put(struct dp83640_clock *clock) argument 1081 struct dp83640_clock *clock; local 1136 struct dp83640_clock *clock; local 1171 struct dp83640_clock *clock = dp83640->clock; local [all...] |
/drivers/media/platform/s5p-mfc/ |
H A D | s5p_mfc_pm.c | 44 mfc_err("Failed to get clock-gating control\n"); 51 mfc_err("Failed to prepare clock-gating control\n"); 56 pm->clock = clk_get(&dev->plat_dev->dev, MFC_SCLK_NAME); 57 if (IS_ERR(pm->clock)) { 58 mfc_info("Failed to get MFC special clock control\n"); 60 clk_set_rate(pm->clock, MFC_SCLK_RATE); 61 ret = clk_prepare_enable(pm->clock); 63 mfc_err("Failed to enable MFC special clock\n"); 80 clk_put(pm->clock); 90 pm->clock) { [all...] |
/drivers/video/fbdev/vermilion/ |
H A D | cr_pll.c | 100 static int crvml_nearest_index(const struct vml_sys *sys, int clock) argument 107 cur_diff = clock - crvml_clocks[0]; 110 diff = clock - crvml_clocks[i]; 120 static int crvml_nearest_clock(const struct vml_sys *sys, int clock) argument 122 return crvml_clocks[crvml_nearest_index(sys, clock)]; 125 static int crvml_set_clock(struct vml_sys *sys, int clock) argument 131 index = crvml_nearest_index(sys, clock); 133 if (crvml_clocks[index] != clock)
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/drivers/gpu/drm/nouveau/core/subdev/clock/ |
H A D | nva3.h | 4 #include <subdev/clock.h>
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H A D | nv50.h | 6 #include <subdev/clock.h>
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/drivers/mmc/host/ |
H A D | sdhci-cns3xxx.c | 26 static void sdhci_cns3xxx_set_clock(struct sdhci_host *host, unsigned int clock) argument 37 if (clock == 0) 40 while (host->max_clk / div > clock) { 53 dev_dbg(dev, "desired SD clock: %d, actual: %d\n", 54 clock, host->max_clk / div); 68 dev_warn(dev, "clock is unstable");
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/drivers/video/fbdev/matrox/ |
H A D | matroxfb_maven.h | 16 unsigned int clock; member in struct:i2c_bit_adapter::__anon7156
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/drivers/media/platform/exynos4-is/ |
H A D | fimc-is-i2c.c | 23 struct clk *clock; member in struct:fimc_is_i2c 44 isp_i2c->clock = devm_clk_get(&pdev->dev, "i2c_isp"); 45 if (IS_ERR(isp_i2c->clock)) { 46 dev_err(&pdev->dev, "failed to get the clock\n"); 47 return PTR_ERR(isp_i2c->clock); 89 clk_disable_unprepare(isp_i2c->clock); 97 return clk_prepare_enable(isp_i2c->clock);
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/drivers/clk/hisilicon/ |
H A D | clk-hip04.c | 2 * Hisilicon HiP04 clock driver 35 #include <dt-bindings/clock/hip04-clock.h> 58 CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);
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/drivers/gpu/drm/mgag200/ |
H A D | mgag200_i2c.c | 71 mga_i2c_set(mdev, i2c->clock, state); 85 return (mga_i2c_read_gpio(mdev) & i2c->clock) ? 1 : 0; 93 int data, clock; local 105 clock = 2; 110 clock = 1; 114 clock = 8; 123 i2c->clock = clock;
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/drivers/gpu/drm/shmobile/ |
H A D | shmob_drm_drv.h | 33 struct clk *clock; member in struct:shmob_drm_device
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/drivers/ptp/ |
H A D | Kconfig | 2 # PTP clock support configuration 5 menu "PTP clock support" 8 tristate "PTP clock support" 22 devices. If you want to use a PTP clock, then you should 23 also enable at least one clock driver as well. 29 tristate "Freescale eTSEC as PTP clock" 35 clock. This clock is only useful if your PTP programs are 43 tristate "Intel IXP46x as PTP clock" 49 clock [all...] |