Searched refs:mb (Results 1 - 25 of 258) sorted by relevance

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/drivers/staging/line6/
H A Dmidibuf.h24 extern int line6_midibuf_bytes_used(struct midi_buffer *mb);
25 extern int line6_midibuf_bytes_free(struct midi_buffer *mb);
26 extern void line6_midibuf_destroy(struct midi_buffer *mb);
27 extern int line6_midibuf_ignore(struct midi_buffer *mb, int length);
28 extern int line6_midibuf_init(struct midi_buffer *mb, int size, int split);
29 extern int line6_midibuf_read(struct midi_buffer *mb, unsigned char *data,
31 extern void line6_midibuf_reset(struct midi_buffer *mb);
32 extern int line6_midibuf_skip_message(struct midi_buffer *mb,
34 extern void line6_midibuf_status(struct midi_buffer *mb);
35 extern int line6_midibuf_write(struct midi_buffer *mb, unsigne
[all...]
/drivers/power/
H A Dipaq_micro_battery.c54 struct micro_battery *mb = container_of(work, local
64 ipaq_micro_tx_msg_sync(mb->micro, &msg_battery);
78 mb->ac = msg_battery.rx_data[0];
79 mb->chemistry = msg_battery.rx_data[1];
80 mb->voltage = ((((unsigned short)msg_battery.rx_data[3] << 8) +
82 mb->flag = msg_battery.rx_data[4];
88 ipaq_micro_tx_msg_sync(mb->micro, &msg_sensor);
89 mb->temperature = msg_sensor.rx_data[1] << 8 | msg_sensor.rx_data[0];
91 queue_delayed_work(mb->wq, &mb
96 struct micro_battery *mb = dev_get_drvdata(b->dev->parent); local
116 struct micro_battery *mb = dev_get_drvdata(b->dev->parent); local
135 struct micro_battery *mb = dev_get_drvdata(b->dev->parent); local
183 struct micro_battery *mb = dev_get_drvdata(b->dev->parent); local
228 struct micro_battery *mb; local
249 struct micro_battery *mb = platform_get_drvdata(pdev); local
260 struct micro_battery *mb = dev_get_drvdata(dev); local
268 struct micro_battery *mb = dev_get_drvdata(dev); local
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/drivers/scsi/lpfc/
H A Dlpfc_mbox.c60 MAILBOX_t *mb; local
63 mb = &pmb->u.mb;
67 mb->mbxCommand = MBX_DUMP_MEMORY;
68 mb->un.varDmp.type = DMP_NV_PARAMS;
69 mb->un.varDmp.entry_index = offset;
70 mb->un.varDmp.region_id = DMP_REGION_VPORT;
71 mb->mbxOwner = OWN_HOST;
75 mb->un.varDmp.cv = 1;
76 mb
113 MAILBOX_t *mb; local
136 MAILBOX_t *mb; local
168 MAILBOX_t *mb; local
205 MAILBOX_t *mb; local
231 MAILBOX_t *mb; local
257 MAILBOX_t *mb; local
291 MAILBOX_t *mb; local
330 MAILBOX_t *mb; local
359 MAILBOX_t *mb = &pmb->u.mb; local
405 MAILBOX_t *mb = &pmb->u.mb; local
487 MAILBOX_t *mb; local
587 MAILBOX_t *mb; local
642 MAILBOX_t *mb; local
674 MAILBOX_t *mb; local
699 MAILBOX_t *mb; local
737 MAILBOX_t *mb = &pmb->u.mb; local
801 MAILBOX_t *mb; local
870 MAILBOX_t *mb = &pmb->u.mb; local
917 MAILBOX_t *mb = &pmb->u.mb; local
1015 MAILBOX_t *mb = &pmb->u.mb; local
1027 MAILBOX_t *mb = &pmb->u.mb; local
1128 MAILBOX_t *mb = &pmb->u.mb; local
1203 MAILBOX_t *mb = &pmb->u.mb; local
1258 MAILBOX_t *mb = &pmb->u.mb; local
1446 MAILBOX_t *mb = &pmb->u.mb; local
2225 MAILBOX_t *mb; local
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/drivers/scsi/qla2xxx/
H A Dqla_mbx.c23 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
80 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
95 mcp->mb[0]);
104 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
116 iptr = mcp->mb;
117 command = mcp->mb[0];
234 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
246 iptr2 = mcp->mb;
277 "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
285 if (mcp->mb[
1844 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) argument
1983 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) argument
3127 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma, uint16_t buffers, uint16_t *mb, uint32_t *dwords) argument
3227 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t *port_speed, uint16_t *mb) argument
3270 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t port_speed, uint16_t *mb) argument
3899 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb) argument
4597 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb) argument
4695 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb) argument
4730 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb) argument
4760 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority, uint16_t *mb) argument
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H A Dqla_isr.c40 uint16_t mb[4]; local
84 mb[0] = RD_MAILBOX_REG(ha, reg, 0);
85 if (mb[0] > 0x3fff && mb[0] < 0x8000) {
86 qla2x00_mbx_completion(vha, mb[0]);
88 } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
89 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
90 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
91 mb[
159 uint16_t mb[4]; local
305 uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS]; local
377 qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb) argument
569 qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb) argument
2659 uint16_t mb[8]; local
2829 uint16_t mb[8]; local
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/drivers/net/ethernet/apple/
H A Dmacmace.c269 volatile struct mace *mb = mp->mace; local
275 mb->biucc = SWRST;
276 if (mb->biucc & SWRST) {
287 mb->maccc = 0; /* turn off tx, rx */
288 mb->imr = 0xFF; /* disable all intrs for now */
289 i = mb->ir;
291 mb->biucc = XMTSP_64;
292 mb->utr = RTRD;
293 mb->fifocc = XMTFW_8 | RCVFW_64 | XMTFWU | RCVFWU;
295 mb
326 volatile struct mace *mb = mp->mace; local
347 volatile struct mace *mb = mp->mace; local
372 volatile struct mace *mb = mp->mace; local
435 volatile struct mace *mb = mp->mace; local
487 volatile struct mace *mb = mp->mace; local
538 volatile struct mace *mb = mp->mace; local
561 volatile struct mace *mb = mp->mace; local
612 volatile struct mace *mb = mp->mace; local
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H A Dmace.c320 volatile struct mace __iomem *mb = mp->mace; local
326 out_8(&mb->biucc, SWRST);
327 if (in_8(&mb->biucc) & SWRST) {
338 out_8(&mb->imr, 0xff); /* disable all intrs for now */
339 i = in_8(&mb->ir);
340 out_8(&mb->maccc, 0); /* turn off tx, rx */
342 out_8(&mb->biucc, XMTSP_64);
343 out_8(&mb->utr, RTRD);
344 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
345 out_8(&mb
375 volatile struct mace __iomem *mb = mp->mace; local
396 volatile struct mace __iomem *mb = mp->mace; local
431 volatile struct mace __iomem *mb = mp->mace; local
501 volatile struct mace __iomem *mb = mp->mace; local
589 volatile struct mace __iomem *mb = mp->mace; local
640 volatile struct mace __iomem *mb = mp->mace; local
663 volatile struct mace __iomem *mb = mp->mace; local
809 volatile struct mace __iomem *mb = mp->mace; local
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/drivers/gpu/drm/
H A Ddrm_cache.c62 mb();
65 mb();
116 mb();
119 mb();
139 mb();
143 mb();
/drivers/media/pci/ivtv/
H A Divtv-mailbox.c145 static int try_mailbox(struct ivtv *itv, struct ivtv_mailbox_data *mbdata, int mb) argument
147 u32 flags = readl(&mbdata->mbox[mb].flags);
151 if (is_free && !test_and_set_bit(mb, &mbdata->busy)) {
152 write_sync(IVTV_MBOX_DRIVER_BUSY, &mbdata->mbox[mb].flags);
163 int i, mb; local
174 for (mb = 1; mb <= max_mbox; mb++)
175 if (try_mailbox(itv, mbdata, mb))
176 return mb;
219 int flags, mb, i; local
372 ivtv_api_get_data(struct ivtv_mailbox_data *mbdata, int mb, int argc, u32 data[]) argument
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H A Divtv-mailbox.h27 void ivtv_api_get_data(struct ivtv_mailbox_data *mbdata, int mb,
/drivers/net/fddi/skfp/
H A Dhwmtm.c78 static void queue_llc_rx(struct s_smc *smc, SMbuf *mb);
79 static void smt_to_llc(struct s_smc *smc, SMbuf *mb);
82 static void queue_txd_mb(struct s_smc *smc, SMbuf *mb);
141 void smt_free_mbuf(struct s_smc *smc, SMbuf *mb);
281 smc->os.hwm.mbuf_pool.mb_start=(SMbuf *)(&smc->os.hwm.mbuf_pool.mb[0]) ;
424 SMbuf *mb ; local
434 mb = smc->os.hwm.mbuf_pool.mb_start ;
437 mb->sm_use_count = 1 ;
438 smt_free_mbuf(smc,mb) ;
439 mb
488 register SMbuf *mb ; local
508 smt_free_mbuf(struct s_smc *smc, SMbuf *mb) argument
713 SMbuf *mb ; local
1055 SMbuf *mb ; local
1380 smt_to_llc(struct s_smc *smc, SMbuf *mb) argument
1734 queue_llc_rx(struct s_smc *smc, SMbuf *mb) argument
1760 SMbuf *mb ; local
1774 queue_txd_mb(struct s_smc *smc, SMbuf *mb) argument
1793 SMbuf *mb ; local
1806 smt_send_mbuf(struct s_smc *smc, SMbuf *mb, int fc) argument
1946 SMbuf *mb ; local
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H A Dsmt.c34 #define m_fc(mb) ((mb)->sm_data[0])
81 static void smt_add_frame_len(SMbuf *mb, int len);
469 void smt_received_pack(struct s_smc *smc, SMbuf *mb, int fs) argument
477 switch (m_fc(mb)) {
484 smt_free_mbuf(smc,mb) ;
489 sm = smtod(mb,struct smt_header *) ;
495 smt_free_mbuf(smc,mb) ;
501 smt_free_mbuf(smc,mb) ;
506 smt_swap_para(sm,(int) mb
833 smt_send_frame(struct s_smc *smc, SMbuf *mb, int fc, int local) argument
862 SMbuf *mb ; local
941 SMbuf *mb ; local
1008 SMbuf *mb ; local
1031 SMbuf *mb ; local
1064 SMbuf *mb ; local
1109 SMbuf *mb ; local
1142 smt_add_frame_len(SMbuf *mb, int len) argument
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H A Dess.c87 static void ess_send_frame(struct s_smc *smc, SMbuf *mb);
103 int ess_raf_received_pack(struct s_smc *smc, SMbuf *mb, struct smt_header *sm,
117 int ess_raf_received_pack(struct s_smc *smc, SMbuf *mb, struct smt_header *sm, argument
207 db->sm_len = mb->sm_len ;
208 db->sm_off = mb->sm_off ;
478 SMbuf *mb ; local
485 if (!(mb=smt_build_frame(smc,SMT_RAF,SMT_REPLY,
490 if (!(mb=smt_build_frame(smc,SMT_RAF,SMT_REPLY,
495 chg = smtod(mb,struct smt_sba_chg *) ;
536 ess_send_frame(smc,mb) ;
556 SMbuf *mb ; local
661 ess_send_frame(struct s_smc *smc, SMbuf *mb) argument
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/drivers/media/pci/cx18/
H A Dcx18-mailbox.c119 static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name) argument
127 "\n", name, mb->request, mb->ack, mb->cmd, mb->error,
128 u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr));
247 struct cx18_mailbox *mb; local
253 mb = &order->mb;
254 handle = mb
436 struct cx18_mailbox *mb; local
539 struct cx18_mailbox __iomem *mb; local
604 struct cx18_mailbox __iomem *mb; local
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/drivers/scsi/
H A Dqla1280.c1146 uint16_t mb[MAILBOX_REGISTER_COUNT]; local
1155 mb[0] = MBC_SET_TARGET_PARAMETERS;
1156 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
1157 mb[2] = nv->bus[bus].target[target].parameter.renegotiate_on_error << 8;
1158 mb[2] |= nv->bus[bus].target[target].parameter.stop_queue_on_check << 9;
1159 mb[2] |= nv->bus[bus].target[target].parameter.auto_request_sense << 10;
1160 mb[2] |= nv->bus[bus].target[target].parameter.tag_queuing << 11;
1161 mb[2] |= nv->bus[bus].target[target].parameter.enable_sync << 12;
1162 mb[2] |= nv->bus[bus].target[target].parameter.enable_wide << 13;
1163 mb[
1594 uint16_t mb[MAILBOX_REGISTER_COUNT]; local
1709 uint16_t mb[MAILBOX_REGISTER_COUNT], i; local
1748 uint16_t mb[MAILBOX_REGISTER_COUNT], cnt; local
1853 uint16_t mb[MAILBOX_REGISTER_COUNT]; local
1918 uint16_t mb[MAILBOX_REGISTER_COUNT]; local
2104 uint16_t mb[MAILBOX_REGISTER_COUNT]; local
2162 uint16_t mb[MAILBOX_REGISTER_COUNT]; local
2196 uint16_t mb[MAILBOX_REGISTER_COUNT]; local
2460 qla1280_mailbox_command(struct scsi_qla_host *ha, uint8_t mr, uint16_t *mb) argument
2593 uint16_t mb[MAILBOX_REGISTER_COUNT]; local
2653 uint16_t mb[MAILBOX_REGISTER_COUNT]; local
2687 uint16_t mb[MAILBOX_REGISTER_COUNT]; local
3968 uint16_t mb[MAILBOX_REGISTER_COUNT]; local
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H A Daha1542.c132 struct mailbox mb[2 * AHA1542_MAILBOXES]; member in struct:aha1542_hostdata
407 struct mailbox *mb; local
410 mb = HOSTDATA(shost)->mb;
458 if (mb[mbi].status != 0)
465 if (mb[mbi].status == 0) {
477 mbo = (scsi2int(mb[mbi].ccbptr) - (SCSI_BUF_PA(&ccb[0]))) / sizeof(struct ccb);
478 mbistatus = mb[mbi].status;
479 mb[mbi].status = 0;
487 ccb[mbo].tarstat + ((int) ccb[mbo].hastat << 16), mb[mb
568 struct mailbox *mb; local
724 struct mailbox *mb; local
1229 struct mailbox *mb; local
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H A Da3000.c101 mb(); /* make sure setup is completed */
103 mb(); /* make sure DMA has started before next IO */
123 mb(); /* make sure CNTR is updated before next IO */
128 mb(); /* don't allow prefetch */
131 mb(); /* no IO until FLUSH is done */
142 mb(); /* make sure DMA is stopped before next IO */
146 mb(); /* make sure CNTR is updated before next IO */
/drivers/video/fbdev/
H A Dbt455.h28 mb();
39 mb();
73 mb();
H A Dbt431.h82 mb();
97 mb();
109 mb();
134 mb();
146 mb();
/drivers/parport/
H A Dparport_amiga.c42 mb();
119 mb();
126 mb();
139 mb();
144 mb();
149 mb();
154 mb();
202 mb();
/drivers/net/can/
H A Dat91_can.c305 unsigned int mb, enum at91_mb_mode mode, int prio)
307 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
310 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, argument
313 set_mb_mode_prio(priv, mb, mode, 0);
472 * (mb - get_mb_tx_first(priv));
480 unsigned int mb, prio; local
486 mb = get_tx_next_mb(priv);
489 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
500 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
501 at91_write(priv, AT91_MID(mb), reg_mi
304 set_mb_mode_prio(const struct at91_priv *priv, unsigned int mb, enum at91_mb_mode mode, int prio) argument
554 at91_activate_rx_mb(const struct at91_priv *priv, unsigned int mb) argument
596 at91_read_mb(struct net_device *dev, unsigned int mb, struct can_frame *cf) argument
633 at91_read_msg(struct net_device *dev, unsigned int mb) argument
708 unsigned int mb; local
860 unsigned int mb; local
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/drivers/target/
H A Dtarget_core_user.c98 /* Offset of data ring from start of mb */
241 struct tcmu_mailbox *mb = udev->mb_addr; local
246 tcmu_flush_dcache_range(mb, sizeof(*mb));
248 cmd_head = mb->cmd_head % udev->cmdr_size; /* UAM */
281 struct tcmu_mailbox *mb; local
310 mb = udev->mb_addr;
311 cmd_head = mb->cmd_head % udev->cmdr_size; /* UAM */
336 cmd_head = mb->cmd_head % udev->cmdr_size; /* UAM */
343 entry = (void *) mb
519 struct tcmu_mailbox *mb; local
807 struct tcmu_mailbox *mb; local
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/drivers/scsi/csiostor/
H A Dcsio_mb.c60 hdr = (struct fw_cmd_hdr *)(mbp->mb);
80 struct fw_hello_cmd *cmdp = (struct fw_hello_cmd *)(mbp->mb);
112 struct fw_hello_cmd *rsp = (struct fw_hello_cmd *)(mbp->mb);
143 struct fw_bye_cmd *cmdp = (struct fw_bye_cmd *)(mbp->mb);
166 struct fw_reset_cmd *cmdp = (struct fw_reset_cmd *)(mbp->mb);
200 struct fw_params_cmd *cmdp = (struct fw_params_cmd *)(mbp->mb);
244 struct fw_params_cmd *rsp = (struct fw_params_cmd *)(mbp->mb);
266 struct fw_ldst_cmd *ldst_cmd = (struct fw_ldst_cmd *)(mbp->mb);
305 (struct fw_caps_config_cmd *)(mbp->mb);
349 struct fw_port_cmd *cmdp = (struct fw_port_cmd *)(mbp->mb);
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/drivers/net/wireless/brcm80211/brcmsmac/
H A Dtypes.h268 #define mboolset(mb, bit) ((mb) |= (bit))
270 #define mboolclr(mb, bit) ((mb) &= ~(bit))
272 #define mboolisset(mb, bit) (((mb) & (bit)) != 0)
273 #define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
/drivers/isdn/hisax/
H A Disurf.c45 writeb(value, cs->hw.isurf.isac + offset); mb();
61 writeb(data[i], cs->hw.isurf.isac); mb();
80 writeb(value, cs->hw.isurf.isar + offset); mb();
115 writeb(0, cs->hw.isurf.isar + ISAR_IRQBIT); mb();
116 writeb(0xFF, cs->hw.isurf.isac + ISAC_MASK); mb();
117 writeb(0, cs->hw.isurf.isac + ISAC_MASK); mb();
118 writeb(ISAR_IRQMSK, cs->hw.isurf.isar + ISAR_IRQBIT); mb();
160 writeb(0, cs->hw.isurf.isar + ISAR_IRQBIT); mb();

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