Searched refs:mmio (Results 1 - 25 of 194) sorted by relevance

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/drivers/net/ethernet/amd/
H A Damd8111e.c115 void __iomem *mmio = lp->mmio; local
119 reg_val = readl(mmio + PHY_ACCESS);
121 reg_val = readl( mmio + PHY_ACCESS );
124 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
126 reg_val = readl(mmio + PHY_ACCESS);
145 void __iomem *mmio = lp->mmio; local
148 reg_val = readl(mmio + PHY_ACCESS);
150 reg_val = readl( mmio
378 void __iomem *mmio = lp->mmio; local
434 void __iomem *mmio = lp->mmio; local
512 void __iomem *mmio = lp->mmio; local
695 void __iomem *mmio = lp->mmio; local
865 amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER) argument
888 void __iomem *mmio = lp->mmio; local
1122 void __iomem *mmio = lp->mmio; local
1335 void __iomem *mmio = lp->mmio; local
1697 void __iomem *mmio = lp->mmio; local
[all...]
/drivers/video/fbdev/i810/
H A Di810_main.c160 * @mmio: address of register space
166 static void i810_screen_off(u8 __iomem *mmio, u8 mode) argument
171 i810_writeb(SR_INDEX, mmio, SR01);
172 val = i810_readb(SR_DATA, mmio);
176 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--);
177 i810_writeb(SR_INDEX, mmio, SR01);
178 i810_writeb(SR_DATA, mmio, val);
183 * @mmio: address of register space
190 static void i810_dram_off(u8 __iomem *mmio, u8 mode) argument
194 val = i810_readb(DRAMCH, mmio);
209 i810_protect_regs(u8 __iomem *mmio, int mode) argument
232 u8 __iomem *mmio = par->mmio_start_virtual; local
257 u8 __iomem *mmio = par->mmio_start_virtual; local
300 u8 __iomem *mmio = par->mmio_start_virtual; local
327 u8 __iomem *mmio = par->mmio_start_virtual; local
347 i810_hires(u8 __iomem *mmio) argument
370 u8 __iomem *mmio = par->mmio_start_virtual; local
400 u8 __iomem *mmio = par->mmio_start_virtual; local
422 u8 __iomem *mmio = par->mmio_start_virtual; local
439 i810_write_dac(u8 regno, u8 red, u8 green, u8 blue, u8 __iomem *mmio) argument
448 i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue, u8 __iomem *mmio) argument
463 u8 __iomem *mmio = par->mmio_start_virtual; local
483 u8 __iomem *mmio = par->mmio_start_virtual; local
495 u8 __iomem *mmio = par->mmio_start_virtual; local
529 u8 __iomem *mmio = par->mmio_start_virtual; local
544 u8 __iomem *mmio = par->mmio_start_virtual; local
558 u8 __iomem *mmio = par->mmio_start_virtual; local
587 u8 __iomem *mmio = par->mmio_start_virtual; local
610 u8 __iomem *mmio = par->mmio_start_virtual; local
634 u8 __iomem *mmio = par->mmio_start_virtual; local
648 u8 __iomem *mmio = par->mmio_start_virtual; local
771 i810_enable_cursor(u8 __iomem *mmio, int mode) argument
821 u8 __iomem *mmio = par->mmio_start_virtual; local
851 u8 __iomem *mmio = par->mmio_start_virtual; local
1202 u8 __iomem *mmio = par->mmio_start_virtual; local
1285 u8 __iomem *mmio = par->mmio_start_virtual; local
1391 u8 __iomem *mmio = par->mmio_start_virtual; local
1480 u8 __iomem *mmio = par->mmio_start_virtual; local
1817 u8 __iomem *mmio = par->mmio_start_virtual; local
[all...]
H A Di810-i2c.c46 u8 __iomem *mmio = par->mmio_start_virtual; local
49 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK);
51 i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);
52 i810_readl(mmio, chan->ddc_base); /* flush posted write */
59 u8 __iomem *mmio = par->mmio_start_virtual; local
62 i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK);
64 i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK);
65 i810_readl(mmio, chan->ddc_base); /* flush posted write */
72 u8 __iomem *mmio = par->mmio_start_virtual; local
74 i810_writel(mmio, cha
83 u8 __iomem *mmio = par->mmio_start_virtual; local
[all...]
H A Di810_accel.c36 static inline void i810_report_error(u8 __iomem *mmio) argument
43 i810_readw(IIR, mmio),
44 i810_readb(EIR, mmio),
45 i810_readl(PGTBL_ER, mmio),
46 i810_readl(IPEIR, mmio),
47 i810_readl(IPEHR, mmio));
63 u8 __iomem *mmio = par->mmio_start_virtual; local
67 head = i810_readl(IRING + 4, mmio) & RBUFFER_HEAD_MASK;
76 i810_report_error(mmio);
93 u8 __iomem *mmio local
137 u8 __iomem *mmio = par->mmio_start_virtual; local
287 u8 __iomem *mmio = par->mmio_start_virtual; local
418 u8 __iomem *mmio = par->mmio_start_virtual; local
439 u8 __iomem *mmio = par->mmio_start_virtual; local
[all...]
/drivers/staging/comedi/drivers/
H A Dni_pcidio.c315 dev->mmio + DMA_Line_Control_Group1);
334 dev->mmio + DMA_Line_Control_Group1);
406 status = readb(dev->mmio + Interrupt_And_Window_Status);
407 flags = readb(dev->mmio + Group_1_Flags);
436 dev->mmio + Master_DMA_And_Interrupt_Control);
448 writeb(0x00, dev->mmio +
453 auxdata = readl(dev->mmio + Group_1_FIFO);
458 flags = readb(dev->mmio + Group_1_Flags);
464 writeb(ClearExpired, dev->mmio + Group_1_Second_Clear);
467 writeb(0x00, dev->mmio
[all...]
H A Drtd520.c494 writel(0, dev->mmio + LAS0_CGT_CLEAR);
495 writel(1, dev->mmio + LAS0_CGT_ENABLE);
498 dev->mmio + LAS0_CGT_WRITE);
501 writel(0, dev->mmio + LAS0_CGT_ENABLE);
503 dev->mmio + LAS0_CGL_WRITE);
516 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
519 writel(0, dev->mmio + LAS0_ADC_CONVERSION);
524 writew(0, dev->mmio + LAS0_ADC);
526 fifo_status = readl(dev->mmio + LAS0_ADC);
536 writel(0, dev->mmio
[all...]
H A Dme_daq.c210 writew(devpriv->control_2, dev->mmio + ME_CONTROL_2);
220 void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A;
221 void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B;
255 status = readw(dev->mmio + ME_STATUS);
275 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
279 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
282 writew(0x00, dev->mmio + ME_RESET_INTERRUPT);
286 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
293 writew(val & 0xff, dev->mmio + ME_CHANNEL_LIST);
297 writew(dev_private->control_1, dev->mmio
[all...]
H A Dicp_multi.c164 writew(devpriv->AdcCmdStatus, dev->mmio + ICP_MULTI_ADC_CSR);
175 status = readw(dev->mmio + ICP_MULTI_ADC_CSR);
192 writew(devpriv->IntEnable, dev->mmio + ICP_MULTI_INT_EN);
196 writew(devpriv->IntStatus, dev->mmio + ICP_MULTI_INT_STAT);
204 writew(devpriv->AdcCmdStatus, dev->mmio + ICP_MULTI_ADC_CSR);
214 data[n] = (readw(dev->mmio + ICP_MULTI_AI) >> 4) & 0x0fff;
219 writew(devpriv->IntEnable, dev->mmio + ICP_MULTI_INT_EN);
223 writew(devpriv->IntStatus, dev->mmio + ICP_MULTI_INT_STAT);
235 status = readw(dev->mmio + ICP_MULTI_DAC_CSR);
253 writew(devpriv->IntEnable, dev->mmio
[all...]
H A Dni_6527.c103 writeb(val & 0xff, dev->mmio + NI6527_FILT_INTERVAL_REG(0));
105 dev->mmio + NI6527_FILT_INTERVAL_REG(1));
107 dev->mmio + NI6527_FILT_INTERVAL_REG(2));
109 writeb(NI6527_CLR_INTERVAL, dev->mmio + NI6527_CLR_REG);
118 writeb(val & 0xff, dev->mmio + NI6527_FILT_ENA_REG(0));
119 writeb((val >> 8) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(1));
120 writeb((val >> 16) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(2));
164 val = readb(dev->mmio + NI6527_DI_REG(0));
165 val |= (readb(dev->mmio + NI6527_DI_REG(1)) << 8);
166 val |= (readb(dev->mmio
[all...]
H A Ddt3000.c259 writew(cmd, dev->mmio + DPR_Command_Mbx);
262 status = readw(dev->mmio + DPR_Command_Mbx);
277 writew(subsys, dev->mmio + DPR_SubSys);
279 writew(chan, dev->mmio + DPR_Params(0));
280 writew(gain, dev->mmio + DPR_Params(1));
284 return readw(dev->mmio + DPR_Params(2));
290 writew(subsys, dev->mmio + DPR_SubSys);
292 writew(chan, dev->mmio + DPR_Params(0));
293 writew(0, dev->mmio + DPR_Params(1));
294 writew(data, dev->mmio
[all...]
/drivers/ata/
H A Dsata_sx4.c458 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; local
469 mmio += PDC_CHIP0_OFS;
507 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
511 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
518 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; local
526 mmio += PDC_CHIP0_OFS;
542 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
546 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
569 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
572 mmio
642 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
702 pdc20621_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc, unsigned int doing_hdma, void __iomem *mmio) argument
855 void __iomem *mmio = ap->ioaddr.cmd_addr; local
869 void __iomem *mmio = ap->ioaddr.cmd_addr; local
886 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; local
1004 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1056 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1102 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1161 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1224 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1277 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1406 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
[all...]
H A Dahci_mvebu.c35 writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i));
36 writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i));
37 writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i));
45 hpriv->mmio + AHCI_WINDOW_CTRL(i));
46 writel(cs->base, hpriv->mmio + AHCI_WINDOW_BASE(i));
48 hpriv->mmio + AHCI_WINDOW_SIZE(i));
59 writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
60 writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
H A Dahci_xgene.c198 void __iomem *mmio = ctx->hpriv->mmio; local
201 dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
202 mmio, channel);
203 val = readl(mmio + PORTCFG);
205 writel(val, mmio + PORTCFG);
206 readl(mmio + PORTCFG); /* Force a barrier */
208 writel(0x0001fffe, mmio + PORTPHY1CFG);
209 readl(mmio + PORTPHY1CFG); /* Force a barrier */
210 writel(0x28183219, mmio
[all...]
H A Dahci_imx.c76 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) argument
83 crval = readl(mmio + IMX_P0PHYCR);
88 writel(crval, mmio + IMX_P0PHYCR);
92 srval = readl(mmio + IMX_P0PHYSR);
101 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio) argument
107 writel(crval, mmio + IMX_P0PHYCR);
110 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
115 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
122 static int imx_phy_reg_write(u16 val, void __iomem *mmio) argument
128 writel(crval, mmio
164 imx_phy_reg_read(u16 *val, void __iomem *mmio) argument
186 void __iomem *mmio = hpriv->mmio; local
304 void __iomem *mmio = hpriv->mmio; local
[all...]
/drivers/phy/
H A Dphy-qcom-ipq806x-sata.c27 void __iomem *mmio; member in struct:qcom_ipq806x_sata_phy
67 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
69 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
71 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
76 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
78 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) &
85 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1);
87 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) &
90 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2);
93 reg = readl_relaxed(phy->mmio
[all...]
/drivers/ssb/
H A Dscan.c177 lo = readw(bus->mmio + offset);
178 hi = readw(bus->mmio + offset + 2);
184 return readl(bus->mmio + offset);
207 iounmap(bus->mmio);
211 pci_iounmap(bus->host_pci, bus->mmio);
219 bus->mmio = NULL;
226 void __iomem *mmio = NULL; local
233 mmio = ioremap(baseaddr, SSB_CORE_SIZE);
237 mmio = pci_iomap(bus->host_pci, 0, ~0UL);
244 mmio
275 void __iomem *mmio; local
[all...]
/drivers/video/fbdev/matrox/
H A Dmatroxfb_crtc2.h27 } mmio; member in struct:matroxfb_dh_fb_info
/drivers/gpu/drm/nouveau/core/subdev/devinit/
H A Dnva3.c101 u32 *mmio = nva3_devinit_mmio_part; local
118 while (mmio[0]) {
119 if (addr >= mmio[0] && addr <= mmio[1]) {
120 u32 part = (addr / mmio[2]) & 7;
127 mmio += 3;
144 .mmio = nva3_devinit_mmio,
/drivers/ide/
H A Dide-io-std.c94 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; local
96 if (mmio)
121 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; local
123 if (mmio)
172 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; local
177 if ((io_32bit & 2) && !mmio) {
183 if (mmio)
188 if ((io_32bit & 2) && !mmio)
198 if (mmio)
216 u8 mmio local
[all...]
/drivers/gpu/drm/sis/
H A Dsis_drv.h52 #define SIS_BASE (dev_priv->mmio)
57 drm_local_map_t *mmio; member in struct:drm_sis_private
/drivers/media/pci/mantis/
H A Dmantis_pci.c88 mantis->mmio = ioremap(pci_resource_start(pdev, 0),
91 if (!mantis->mmio) {
107 "irq: %d, latency: %d\n memory: 0x%lx, mmio: 0x%p\n",
111 mantis->mmio);
132 if (mantis->mmio)
133 iounmap(mantis->mmio);
154 dprintk(MANTIS_NOTICE, 1, " mem: 0x%p", mantis->mmio);
156 if (mantis->mmio) {
157 iounmap(mantis->mmio);
/drivers/gpu/drm/nouveau/core/engine/graph/
H A Dgk20a.c46 .mmio = nve4_graph_pack_mmio,
/drivers/gpu/drm/shmobile/
H A Dshmob_drm_drv.h32 void __iomem *mmio; member in struct:shmob_drm_device
/drivers/gpu/drm/rcar-du/
H A Drcar_du_drv.h73 void __iomem *mmio; member in struct:rcar_du_device
101 return ioread32(rcdu->mmio + reg);
106 iowrite32(data, rcdu->mmio + reg);
/drivers/media/platform/vsp1/
H A Dvsp1.h47 void __iomem *mmio; member in struct:vsp1_device
74 return ioread32(vsp1->mmio + reg);
79 iowrite32(data, vsp1->mmio + reg);

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