Searched refs:outpw (Results 1 - 7 of 7) sorted by relevance

/drivers/net/fddi/skfp/
H A Dfplustm.c160 outpw(FM_A(FM_CMDREG1),FM_IRMEMWO) ;
198 outpw(FM_A(FM_RPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* RPR1 */
199 outpw(FM_A(FM_SWPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* SWPR1 */
200 outpw(FM_A(FM_WPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* WPR1 */
201 outpw(FM_A(FM_EARV1),smc->hw.fp.fifo.tx_s_start-1) ; /* EARV1 */
207 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
208 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
209 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
210 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ;
213 outpw(FM_
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H A Dhwt.c82 outpw(ADDR(B2_TI_CRTL), TIM_START) ; /* Start timer. */
103 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ;
104 outpw(ADDR(B2_TI_CRTL), TIM_CL_IRQ) ;
205 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ;
208 outpw(ADDR(B2_TI_CRTL), TIM_START) ;
H A Ddrvfbi.c102 outpw(FM_A(FM_MDREG1),FM_MINIT) ;
118 outpw(PCI_C(PCI_STATUS), word | PCI_ERRBITS) ;
172 outpw(FM_A(FM_MDREG1),FM_MINIT) ;
556 outpw(ADDR(B2_WDOG_CRTL),TIM_START) ; /* Start timer. */
570 outpw(ADDR(B2_WDOG_CRTL),TIM_STOP) ; /* Stop timer. */
H A Dpcmplc.c430 outpw(PLC(p,PL_CNTRL_B),0) ;
431 outpw(PLC(p,PL_CNTRL_B),PL_PCM_STOP) ;
432 outpw(PLC(p,PL_CNTRL_A),0) ;
443 outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_S) ;
445 outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_S) ;
446 outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_S) ;
450 outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_U) ;
452 outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_U) ;
453 outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_U) ;
462 outpw(PL
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/drivers/net/fddi/skfp/h/
H A Dtypes.h36 #define outpw(p,s) iowrite16(s,p) macro
H A Dskfbi.h1036 #define CLEAR(io,mask) outpw((io),inpw(io)&(~(mask)))
1037 #define SET(io,mask) outpw((io),inpw(io)|(mask))
1039 #define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val))
1050 #define MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma))
1051 #define MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma))
1057 #define MDRW(dd) outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\
1058 outpw(FM_A(FM_MDRL),(unsigned int)(dd))
1084 #define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8)
/drivers/scsi/
H A Dadvansys.c128 #define outpw(port, word) outw((word), (port)) macro
883 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
884 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
888 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
890 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
892 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
896 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
901 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
908 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
912 #define AscWriteChipIH(port, data) outpw((por
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