Searched refs:pfit_control (Results 1 - 9 of 9) sorted by relevance
| /drivers/gpu/drm/i915/ |
| H A D | intel_panel.c | 227 u32 *pfit_control)
237 *pfit_control |= PFIT_ENABLE |
240 *pfit_control |= PFIT_ENABLE |
243 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
247 u32 *pfit_control, u32 *pfit_pgm_ratios,
274 *pfit_control |= (PFIT_ENABLE |
290 *pfit_control |= (PFIT_ENABLE |
296 *pfit_control |= (PFIT_ENABLE |
308 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; local
331 i965_scale_aspect(pipe_config, &pfit_control);
226 i965_scale_aspect(struct intel_crtc_config *pipe_config, u32 *pfit_control) argument
246 i9xx_scale_aspect(struct intel_crtc_config *pipe_config, u32 *pfit_control, u32 *pfit_pgm_ratios, u32 *border) argument
[all...] |
| H A D | intel_overlay.c | 849 u32 pfit_control = I915_READ(PFIT_CONTROL); local
859 if (pfit_control & VERT_AUTO_SCALE)
1016 u32 pfit_control; local
1022 pfit_control = I915_READ(PFIT_CONTROL);
1025 if ((pfit_control & PFIT_ENABLE) == 0)
1030 return (pfit_control >> 29) & 0x3;
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| /drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_lvds.c | 360 u32 pfit_control; local
375 pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE |
379 pfit_control = 0;
381 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT;
384 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
386 REG_WRITE(PFIT_CONTROL, pfit_control);
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| H A D | psb_intel_lvds.c | 475 u32 pfit_control; local
490 pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE |
494 pfit_control = 0;
497 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
499 REG_WRITE(PFIT_CONTROL, pfit_control);
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| H A D | oaktrail_crtc.c | 354 u32 pfit_control; local
356 pfit_control = REG_READ(PFIT_CONTROL);
359 if ((pfit_control & PFIT_ENABLE) == 0)
361 return (pfit_control >> 29) & 3;
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| H A D | psb_intel_display.c | 90 u32 pfit_control; local
92 pfit_control = REG_READ(PFIT_CONTROL);
95 if ((pfit_control & PFIT_ENABLE) == 0)
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| H A D | cdv_intel_display.c | 568 u32 pfit_control; local
570 pfit_control = REG_READ(PFIT_CONTROL);
573 if ((pfit_control & PFIT_ENABLE) == 0)
575 return (pfit_control >> 29) & 0x3;
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| H A D | mdfld_intel_display.c | 113 u32 pfit_control; local
115 pfit_control = REG_READ(PFIT_CONTROL);
118 if ((pfit_control & PFIT_ENABLE) == 0)
122 return (pfit_control >> 29) & 0x3;
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| H A D | cdv_intel_dp.c | 897 uint32_t pfit_control; local
902 pfit_control = PFIT_ENABLE;
904 pfit_control = 0;
906 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT;
908 REG_WRITE(PFIT_CONTROL, pfit_control);
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Completed in 135 milliseconds