Searched refs:pll1 (Results 1 - 6 of 6) sorted by relevance
/drivers/gpu/drm/nouveau/core/subdev/devinit/ |
H A D | nv04.c | 201 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; local 208 /* model specific additions to generic pll1 and pll2 set up above */ 210 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | 225 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; 227 if (oldpll1 == pll1 && oldpll2 == pll2) 261 nv_wr32(devinit, reg1, pll1);
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/drivers/clk/sirf/ |
H A D | clk-atlas6.c | 63 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator in enum:atlas6_clk_index 139 for (i = pll1; i < maxclk; i++) {
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H A D | clk-prima2.c | 62 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator in enum:prima2_clk_index 138 for (i = pll1; i < maxclk; i++) {
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/drivers/gpu/drm/tegra/ |
H A D | hdmi.c | 23 u32 pll1; member in struct:tmds_config 169 .pll1 = SOR_PLL_TMDS_TERM_ENABLE, 184 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 202 .pll1 = SOR_PLL_TMDS_TERM_ENABLE, 216 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 230 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 247 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), 265 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 284 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 303 .pll1 [all...] |
/drivers/gpu/drm/nouveau/dispnv04/ |
H A D | hw.c | 132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, argument 140 pllvals->log2P = (pll1 >> 16) & 0x7; 146 if (!(pll1 & 0x1100)) 149 pllvals->NM1 = pll1 & 0xffff; 154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { 155 pllvals->M2 = (pll1 >> 4) & 0x7; 156 pllvals->N2 = ((pll1 >> 21) & 0x18) | 157 ((pll1 >> 19) & 0x7); 170 uint32_t reg1, pll1, pll2 = 0; local 178 pll1 [all...] |
/drivers/clk/mxs/ |
H A D | clk-imx28.c | 139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator in enum:imx28_clk 175 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); 236 clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
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