| /drivers/mfd/ |
| H A D | sm501.c | 117 static unsigned long decode_div(unsigned long pll2, unsigned long val, argument
122 pll2 = 288 * MHZ;
124 return pll2 / div_tab[(val >> lshft) & mask];
141 unsigned long pll2 = 0; local
145 pll2 = 336 * MHZ;
148 pll2 = 288 * MHZ;
151 pll2 = 240 * MHZ;
154 pll2 = 192 * MHZ;
158 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
161 sdclk1 = (misct & (1<<20)) ? pll2
[all...] |
| /drivers/gpu/drm/nouveau/core/subdev/devinit/ |
| H A D | nv04.c | 202 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; local
208 /* model specific additions to generic pll1 and pll2 set up above */
212 pll2 = 0;
221 pll2 |= 0x011f;
227 if (oldpll1 == pll1 && oldpll2 == pll2)
260 nv_wr32(devinit, reg2, pll2);
|
| /drivers/gpu/drm/nouveau/dispnv04/ |
| H A D | hw.c | 133 uint32_t pll2, struct nouveau_pll_vals *pllvals)
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
144 pllvals->NM1 = pll2 & 0xffff;
147 pllvals->NM2 = pll2 >> 16;
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
151 pllvals->NM2 = pll2 & 0xffff;
170 uint32_t reg1, pll1, pll2 = 0; local
180 pll2 = nvif_rd32(device, reg1 + 4);
184 pll2 = nvif_rd32(device, reg2);
193 pll2
132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, uint32_t pll2, struct nouveau_pll_vals *pllvals) argument
[all...] |
| /drivers/clk/sirf/ |
| H A D | clk-atlas6.c | 63 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator in enum:atlas6_clk_index
|
| H A D | clk-prima2.c | 62 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator in enum:prima2_clk_index
|
| /drivers/clk/mxs/ |
| H A D | clk-imx28.c | 139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator in enum:imx28_clk
176 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
237 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
|
| /drivers/clk/qcom/ |
| H A D | mmcc-msm8960.c | 53 "pll2",
66 "pll2",
80 "pll2",
84 static struct clk_pll pll2 = { variable in typeref:struct:clk_pll
93 .name = "pll2",
2368 [PLL2] = &pll2.clkr,
2528 [PLL2] = &pll2.clkr,
|