| /drivers/clk/spear/ |
| H A D | clk-frac-synth.c | 44 static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate, argument
50 prate /= 10000;
51 prate <<= 14;
52 prate /= (2 * rtbl[index].div);
53 prate *= 10000;
55 return prate;
59 unsigned long *prate)
64 return clk_round_rate_index(hw, drate, *prate, frac_calc_rate,
96 unsigned long prate)
103 clk_round_rate_index(hw, drate, prate, frac_calc_rat
58 clk_frac_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
95 clk_frac_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
[all...] |
| H A D | clk-vco-pll.c | 70 unsigned long prate, int index, unsigned long *pll_rate)
72 unsigned long rate = prate;
85 unsigned long *prate, int *index)
92 if (!prate) {
93 pr_err("%s: prate is must for pll clk\n", __func__);
99 vco_prev_rate = *prate;
100 *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,
106 *prate = vco_prev_rate;
117 unsigned long *prate)
121 return clk_pll_round_rate_index(hw, drate, prate,
69 pll_calc_rate(struct pll_rate_tbl *rtbl, unsigned long prate, int index, unsigned long *pll_rate) argument
84 clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate, unsigned long *prate, int *index) argument
116 clk_pll_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
144 clk_pll_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
174 vco_calc_rate(struct clk_hw *hw, unsigned long prate, int index) argument
182 clk_vco_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
230 clk_vco_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
[all...] |
| H A D | clk-gpt-synth.c | 34 static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate, argument
40 prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1));
42 return prate;
46 unsigned long *prate)
51 return clk_round_rate_index(hw, drate, *prate, gpt_calc_rate,
81 unsigned long prate)
88 clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt,
45 clk_gpt_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
80 clk_gpt_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
|
| H A D | clk-aux-synth.c | 44 static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate, argument
51 return (((prate / 10000) * rtbl[index].xscale) /
56 unsigned long *prate)
61 return clk_round_rate_index(hw, drate, *prate, aux_calc_rate,
100 unsigned long prate)
107 clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt,
55 clk_aux_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
99 clk_aux_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
|
| H A D | clk.h | 109 typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
|
| /drivers/clk/ |
| H A D | clk-fractional-divider.c | 46 unsigned long *prate)
52 if (!rate || rate >= *prate)
53 return *prate;
55 div = gcd(*prate, rate);
57 while ((*prate / div) > maxn) {
45 clk_fd_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| H A D | clk-fixed-factor.c | 40 unsigned long *prate)
48 *prate = __clk_round_rate(__clk_get_parent(hw->clk),
52 return (*prate / fix->div) * fix->mult;
39 clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| H A D | clk-vt8500.c | 141 unsigned long *prate)
149 divisor = *prate / rate;
151 /* If prate / rate would be decimal, incr the divisor */
152 if (rate * divisor < *prate)
163 return *prate / divisor;
583 unsigned long *prate)
591 vt8500_find_pll_bits(rate, *prate, &mul, &div1);
592 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
595 wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
596 round_rate = WM8650_BITS_TO_FREQ(*prate, mu
140 vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
582 vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
[all...] |
| H A D | clk-divider.c | 321 unsigned long *prate)
324 div = clk_divider_bestdiv(hw, rate, prate);
326 return DIV_ROUND_UP(*prate, div);
320 clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| H A D | clk-composite.c | 128 unsigned long *prate)
136 return rate_ops->round_rate(rate_hw, rate, prate);
127 clk_composite_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
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| /drivers/clk/mmp/ |
| H A D | clk-frac.c | 35 unsigned long *prate)
43 rate = (((*prate / 10000) * factor->ftbl[i].den) /
82 unsigned long prate)
92 rate = (((prate / 10000) * factor->ftbl[i].den) /
34 clk_factor_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
81 clk_factor_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
|
| /drivers/clk/rockchip/ |
| H A D | clk-pll.c | 66 unsigned long drate, unsigned long *prate)
130 unsigned long prate)
133 u64 nf, nr, no, rate64 = prate;
140 return prate;
158 unsigned long prate)
162 unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
177 __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
224 rockchip_rk3066_pll_set_rate(hw, old_rate, prate);
65 rockchip_pll_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
129 rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) argument
157 rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
|
| /drivers/clk/tegra/ |
| H A D | clk-divider.c | 89 unsigned long *prate)
93 unsigned long output_rate = *prate;
100 return *prate;
88 clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| H A D | clk-audio-sync.c | 32 unsigned long *prate)
31 clk_sync_source_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| H A D | clk-periph.c | 60 unsigned long *prate)
68 return div_ops->round_rate(div_hw, rate, prate);
59 clk_periph_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| /drivers/clk/zynq/ |
| H A D | pll.c | 60 * @prate: Clock frequency of parent clock
64 unsigned long *prate)
68 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
74 return *prate * fbdiv;
63 zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| /drivers/clk/mxs/ |
| H A D | clk-div.c | 51 unsigned long *prate)
55 return div->ops->round_rate(&div->divider.hw, rate, prate);
50 clk_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| H A D | clk-frac.c | 53 unsigned long *prate)
56 unsigned long parent_rate = *prate;
52 clk_frac_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| H A D | clk-ref.c | 68 unsigned long *prate)
70 unsigned long parent_rate = *prate;
67 clk_ref_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| /drivers/clk/shmobile/ |
| H A D | clk-rcar-gen2.c | 72 unsigned long prate = *parent_rate; local
75 if (!prate)
76 prate = 1;
78 mult = div_u64((u64)rate * 32, prate);
|
| /drivers/video/fbdev/omap2/dss/ |
| H A D | dss.c | 432 unsigned long prate; local
452 prate = clk_get_rate(dss.parent_clk);
456 fckd_start = min(prate * m / fck_min, fckd_hw_max);
457 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
460 fck = DIV_ROUND_UP(prate, fckd) * m;
495 unsigned long max_dss_fck, prate; local
505 prate = clk_get_rate(dss.parent_clk);
507 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
509 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
|
| /drivers/clk/st/ |
| H A D | clk-flexgen.c | 104 unsigned long *prate)
108 /* Round div according to exact prate and wished rate */
109 div = clk_best_div(*prate, rate);
112 *prate = rate * div;
116 return *prate / div;
103 flexgen_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| /drivers/staging/imx-drm/ |
| H A D | imx-tve.c | 426 unsigned long *prate)
430 div = *prate / rate;
432 return *prate / 4;
434 return *prate / 2;
435 return *prate;
425 clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| /drivers/clk/ti/ |
| H A D | divider.c | 203 unsigned long *prate)
206 div = ti_clk_divider_bestdiv(hw, rate, prate);
208 return DIV_ROUND_UP(*prate, div);
202 ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
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| /drivers/clk/versatile/ |
| H A D | clk-icst.c | 95 unsigned long *prate)
94 icst_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|