Searched refs:readl_relaxed (Results 1 - 25 of 161) sorted by relevance

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/drivers/crypto/ux500/cryp/
H A Dcryp.c38 peripheralid2 = readl_relaxed(&device_data->base->periphId2);
45 readl_relaxed(&device_data->base->periphId0))
47 readl_relaxed(&device_data->base->periphId1))
49 readl_relaxed(&device_data->base->periphId3))
51 readl_relaxed(&device_data->base->pcellId0))
53 readl_relaxed(&device_data->base->pcellId1))
55 readl_relaxed(&device_data->base->pcellId2))
57 readl_relaxed(&device_data->base->pcellId3))) {
99 while (readl_relaxed(&device_data->base->sr) !=
309 ctx->din = readl_relaxed(
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H A Dcryp_irq.c26 i = readl_relaxed(&device_data->base->imsc);
37 i = readl_relaxed(&device_data->base->imsc);
44 return (readl_relaxed(&device_data->base->mis) & irq_src) > 0;
H A Dcryp_p.h24 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
27 writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
31 (readl_relaxed(reg_name) & (val))
34 writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \
/drivers/clk/mxs/
H A Dclk.c24 while (readl_relaxed(reg) & (1 << shift))
/drivers/irqchip/
H A Dirq-sirfsoc.c55 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
97 sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
98 sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
99 sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
100 sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
/drivers/mtd/nand/
H A Datmel_nand_ecc.h115 readl_relaxed((addr) + ATMEL_PMECC_##reg)
124 readl_relaxed((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4))
127 readl_relaxed((addr) + ATMEL_PMERRLOC_##reg)
136 readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
139 readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
/drivers/gpio/
H A Dgpio-mvebu.c191 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
206 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
207 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
208 readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
210 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
224 u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
248 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
275 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
388 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
408 u = readl_relaxed(mvebu_gpioreg_in_po
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/drivers/clk/berlin/
H A Dberlin2-avpll.c129 reg = readl_relaxed(vco->base + VCO_CTRL0);
141 reg = readl_relaxed(vco->base + VCO_CTRL0);
156 reg = readl_relaxed(vco->base + VCO_CTRL0);
174 reg = readl_relaxed(vco->base + VCO_CTRL1);
231 reg = readl_relaxed(ch->base + VCO_CTRL10);
242 reg = readl_relaxed(ch->base + VCO_CTRL10);
254 reg = readl_relaxed(ch->base + VCO_CTRL10);
269 reg = readl_relaxed(ch->base + VCO_CTRL30);
278 reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index));
284 reg = readl_relaxed(c
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H A Dberlin2-div.c84 reg = readl_relaxed(div->base + map->gate_offs);
102 reg = readl_relaxed(div->base + map->gate_offs);
121 reg = readl_relaxed(div->base + map->gate_offs);
139 reg = readl_relaxed(div->base + map->pll_switch_offs);
148 reg = readl_relaxed(div->base + map->pll_select_offs);
171 reg = readl_relaxed(div->base + map->pll_switch_offs);
174 reg = readl_relaxed(div->base + map->pll_select_offs);
196 divsw = readl_relaxed(div->base + map->div_switch_offs) &
198 div3sw = readl_relaxed(div->base + map->div3_switch_offs) &
210 reg = readl_relaxed(di
[all...]
/drivers/char/hw_random/
H A Dmsm-rng.c58 val = readl_relaxed(rng->base + PRNG_CONFIG);
62 val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
67 val = readl_relaxed(rng->base + PRNG_CONFIG);
71 val = readl_relaxed(rng->base + PRNG_CONFIG);
103 val = readl_relaxed(rng->base + PRNG_STATUS);
107 val = readl_relaxed(rng->base + PRNG_DATA_OUT);
/drivers/thermal/
H A Ddove_thermal.c57 reg = readl_relaxed(priv->control);
73 reg = readl_relaxed(priv->control);
78 reg = readl_relaxed(priv->sensor);
84 reg = readl_relaxed(priv->sensor);
102 reg = readl_relaxed(priv->control + PMU_TEMP_DIOD_CTRL1_REG);
114 reg = readl_relaxed(priv->sensor);
H A Darmada_thermal.c82 reg = readl_relaxed(priv->control);
92 reg = readl_relaxed(priv->control);
98 reg = readl_relaxed(priv->sensor);
108 reg = readl_relaxed(priv->control);
156 unsigned long reg = readl_relaxed(priv->control);
168 unsigned long reg = readl_relaxed(priv->sensor);
187 reg = readl_relaxed(priv->sensor);
/drivers/watchdog/
H A Domap_wdt.c69 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
76 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
87 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
91 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
101 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
105 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
116 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
120 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
136 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
140 while (readl_relaxed(bas
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H A Dsa1100_wdt.c57 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
60 writel_relaxed(readl_relaxed(OIER) | OIER_E3, OIER);
83 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
117 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
132 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
/drivers/clocksource/
H A Dclksrc-dbx500-prcmu.c38 count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
39 count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
H A Dmmio.c25 return (cycle_t)readl_relaxed(to_mmio_clksrc(c)->reg);
30 return ~(cycle_t)readl_relaxed(to_mmio_clksrc(c)->reg) & c->mask;
H A Dtimer-marco.c59 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
66 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
92 writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
95 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
96 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
139 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
154 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
283 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
H A Dtimer-prima2.c64 WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
83 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
85 readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
97 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
102 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
110 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
138 readl_relaxed(sirfsoc_timer_base +
/drivers/phy/
H A Dphy-qcom-ipq806x-sata.c67 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
71 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
78 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) &
87 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) &
93 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
98 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
109 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
122 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
/drivers/soc/tegra/fuse/
H A Dtegra-apbmisc.c36 return readl_relaxed(apbmisc_base + 4);
52 return readl_relaxed(strapping_base);
/drivers/clk/mmp/
H A Dclk-apbc.c49 data = readl_relaxed(apbc->base);
63 data = readl_relaxed(apbc->base);
76 data = readl_relaxed(apbc->base);
96 data = readl_relaxed(apbc->base);
110 data = readl_relaxed(apbc->base);
/drivers/video/fbdev/mmp/hw/
H A Dmmp_spi.c68 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL);
73 isr = readl_relaxed(reg_base + SPU_IRQ_ISR);
76 isr = readl_relaxed(reg_base + SPU_IRQ_ISR);
84 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL);
111 tmp = readl_relaxed(reg_base + SPU_IOPAD_CONTROL);
/drivers/bus/
H A Domap_l3_noc.c92 std_err_main = readl_relaxed(l3_targ_stderr);
99 readl_relaxed(l3_targ_slvofslsb));
121 masterid = (readl_relaxed(l3_targ_mstaddr) &
132 op_code = readl_relaxed(l3_targ_hdr) & 0x7;
134 m_req_info = readl_relaxed(l3_targ_info) & 0xF;
186 err_reg = readl_relaxed(base + flag_mux->offset +
213 mask_val = readl_relaxed(mask_reg);
/drivers/clk/hisilicon/
H A Dclkgate-separated.c59 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
76 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
87 reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
/drivers/clk/tegra/
H A Dclk-pll-out.c33 u32 val = readl_relaxed(pll_out->reg);
51 val = readl_relaxed(pll_out->reg);
73 val = readl_relaxed(pll_out->reg);

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