/drivers/net/ethernet/cirrus/ |
H A D | mac89x0.c | 156 readreg(struct net_device *dev, int portno) function 249 rev_type = readreg(dev, PRODUCT_ID_ADD); 272 if ((readreg(dev, PP_SelfST) & (EEPROM_PRESENT | EEPROM_OK)) == 0) { 278 unsigned short s = readreg(dev, PP_IA + i); 309 writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET); 316 while( (readreg(dev, PP_SelfST) & INIT_DONE) == 0 && jiffies - reset_start_time < 2) 335 writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) & ~ENABLE_IRQ); 352 writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON); 369 writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) | ENABLE_IRQ); 397 if ((readreg(de [all...] |
H A D | cs89x0.c | 221 readreg(struct net_device *dev, u16 regno) function 246 while (readreg(dev, PP_SelfST) & SI_BUSY) 265 buffer[i] = readreg(dev, PP_EEData); 519 writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_TX_ON); 529 if (readreg(dev, PP_BusST) & READY_FOR_TX_NOW) 541 if ((readreg(dev, PP_TxEvent) & TX_SEND_OK_BITS) == TX_OK) { 579 if ((readreg(dev, PP_LineST) & LINK_OK) == 0) 599 readreg(dev, PP_TestCTL) | FDX_8900); 602 fdx = readreg(dev, PP_TestCTL) & FDX_8900; 620 while (readreg(de [all...] |
/drivers/isdn/hisax/ |
H A D | mic.c | 32 readreg(unsigned int ale, unsigned int adr, u_char off) function 68 return (readreg(cs->hw.mic.adr, cs->hw.mic.isac, offset)); 92 return (readreg(cs->hw.mic.adr, 107 #define READHSCX(cs, nr, reg) readreg(cs->hw.mic.adr, \ 128 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40); 132 val = readreg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_ISTA); 136 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40); 142 val = readreg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_ISTA);
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H A D | asuscom.c | 44 readreg(unsigned int ale, unsigned int adr, u_char off) function 80 return (readreg(cs->hw.asus.adr, cs->hw.asus.isac, offset)); 104 return (readreg(cs->hw.asus.adr, cs->hw.asus.isac, offset | 0x80)); 128 return (readreg(cs->hw.asus.adr, 143 #define READHSCX(cs, nr, reg) readreg(cs->hw.asus.adr, \ 164 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); 168 val = readreg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_ISTA); 172 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); 178 val = readreg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_ISTA); 202 ista = readreg(c [all...] |
H A D | bkm_a8.c | 41 readreg(unsigned int ale, unsigned int adr, u_char off) function 80 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80)); 105 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0))); 127 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \ 146 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); 155 val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40); 167 val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80); 176 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); 431 readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
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H A D | bkm_a4t.c | 27 readreg(unsigned int ale, unsigned long adr, u_char off) function 46 *data++ = readreg(ale, adr, off); 76 return (readreg(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, offset)); 100 return (readreg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, offset + (jade == -1 ? 0 : (jade ? 0xC0 : 0x80)))); 113 #define READJADE(cs, nr, reg) readreg(cs->hw.ax.jade_ale, \ 143 val = readreg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, jade_HDLC_ISR + 0x80); 148 val = readreg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, jade_HDLC_ISR + 0xC0); 153 val = readreg(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, ISAC_ISTA);
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H A D | ix1_micro.c | 42 readreg(unsigned int ale, unsigned int adr, u_char off) function 78 return (readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset)); 102 return (readreg(cs->hw.ix1.hscx_ale, 113 #define READHSCX(cs, nr, reg) readreg(cs->hw.ix1.hscx_ale, \ 134 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); 138 val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA); 142 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); 148 val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA);
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H A D | niccy.c | 46 static inline u_char readreg(unsigned int ale, unsigned int adr, u_char off) function 80 return readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset); 100 return readreg(cs->hw.niccy.hscx_ale, 111 #define READHSCX(cs, nr, reg) readreg(cs->hw.niccy.hscx_ale, \ 140 val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, 145 val = readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_ISTA); 149 val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, 156 val = readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_ISTA);
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H A D | s0box.c | 38 readreg(unsigned int padr, signed int addr, u_char off) { function 98 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset)); 122 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset)); 135 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg) 152 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA); 156 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_ISTA); 161 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA); 167 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_ISTA);
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H A D | saphir.c | 34 readreg(unsigned int ale, unsigned int adr, u_char off) function 70 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset)); 94 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, 105 #define READHSCX(cs, nr, reg) readreg(cs->hw.saphir.ale, \ 126 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); 130 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA); 134 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); 140 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA);
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H A D | sedlbauer.c | 120 readreg(unsigned int ale, unsigned int adr, u_char off) function 156 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset)); 180 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset | 0x80)); 204 return (readreg(cs->hw.sedl.adr, 225 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset)); 247 #define READHSCX(cs, nr, reg) readreg(cs->hw.sedl.adr, \ 276 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); 280 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); 284 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); 290 val = readreg(c [all...] |
H A D | avm_a1.c | 29 readreg(unsigned int adr, u_char off) function 58 return (readreg(cs->hw.avm.isac, offset)); 82 return (readreg(cs->hw.avm.hscx[hscx], offset)); 95 #define READHSCX(cs, nr, reg) readreg(cs->hw.avm.hscx[nr], reg) 117 val = readreg(cs->hw.avm.hscx[1], HSCX_ISTA); 122 val = readreg(cs->hw.avm.isac, ISAC_ISTA);
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H A D | teles3.c | 29 readreg(unsigned int adr, u_char off) function 58 return (readreg(cs->hw.teles3.isac, offset)); 82 return (readreg(cs->hw.teles3.hscx[hscx], offset)); 95 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.hscx[nr], reg) 112 val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); 116 val = readreg(cs->hw.teles3.isac, ISAC_ISTA); 121 val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); 127 val = readreg(cs->hw.teles3.isac, ISAC_ISTA);
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H A D | teleint.c | 25 readreg(unsigned int ale, unsigned int adr, u_char off) function 106 return (readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset)); 165 val = readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_ISTA); 169 val = readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_ISTA);
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H A D | elsa.c | 142 readreg(unsigned int ale, unsigned int adr, u_char off) function 178 return (readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset)); 202 return (readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset + 0x80)); 226 return (readreg(cs->hw.elsa.ale, 270 #define READHSCX(cs, nr, reg) readreg(cs->hw.elsa.ale, \ 307 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); 312 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_ISTA); 317 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); 324 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_ISTA); 387 ista = readreg(c [all...] |
H A D | diva.c | 82 readreg(unsigned int ale, unsigned int adr, u_char off) function 134 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset)); 158 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset + 0x80)); 182 return (readreg(cs->hw.diva.hscx_adr, 276 #define READHSCX(cs, nr, reg) readreg(cs->hw.diva.hscx_adr, \ 299 val = readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_ISTA + 0x40); 302 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA); 328 ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA); 333 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, HSCX_ISTA + 0x40); 344 val = 0xfe & readreg(c [all...] |
H A D | gazel.c | 45 readreg(unsigned int adr, u_short off) function 112 return (readreg(cs->hw.gazel.isac, off2)); 207 return (readreg(cs->hw.gazel.hscx[hscx], off2));
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/drivers/media/pci/zoran/ |
H A D | zr36016.c | 80 if (ptr->codec->master_data->readreg) 83 readreg(ptr->codec, reg)) & 0xFF; 124 (ptr->codec->master_data->readreg)) { 126 value = (ptr->codec->master_data->readreg(ptr->codec, ZR016_IDATA)) & 0xFF; // DATA
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H A D | videocodec.h | 82 readreg -> ref. to read-fn from register (setup by master, used by slave) 329 __u32(*readreg) (struct videocodec * codec, 325 __u32(*readreg) (struct videocodec * codec, member in struct:videocodec_master
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H A D | zoran_card.c | 1156 m->readreg = zr36060_read; 1161 m->readreg = zr36050_read; 1166 m->readreg = zr36016_read;
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H A D | zr36050.c | 78 if (ptr->codec->master_data->readreg) 79 value = (ptr->codec->master_data->readreg(ptr->codec,
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H A D | zr36060.c | 82 if (ptr->codec->master_data->readreg) 83 value = (ptr->codec->master_data->readreg(ptr->codec,
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/drivers/ide/ |
H A D | qd65xx.c | 270 u8 savereg, readreg; local 275 readreg = inb_p(port); 286 return (readreg != QD_TESTVAL);
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/drivers/video/fbdev/ |
H A D | gxt4500.c | 140 #define readreg(par, reg) readl((par)->regs + (reg)) macro 392 ctrlreg = readreg(par, DTG_CONTROL); 397 tmp = readreg(par, PLL_C) & ~0x7f; 492 ctrlreg = readreg(par, SYNC_CTL) & 566 ctrl = readreg(par, SYNC_CTL); 568 dctl = readreg(par, DISP_CTL);
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/drivers/net/ethernet/amd/ |
H A D | ni65.c | 161 #define readreg(reg) (outw(reg,PORT+L_ADDRREG),inw(PORT+L_ADDRREG),\ 170 #define readreg(reg) (outw(reg,PORT+L_ADDRREG),inw(PORT+L_DATAREG)) macro 464 if( (j=readreg(CSR0)) != 0x4) { 516 if(readreg(CSR0) & CSR0_IDON) 810 if( (i=readreg(CSR0) ) != 0x4)
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