Searched refs:regval (Results 1 - 25 of 130) sorted by relevance

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/drivers/media/pci/cx23885/
H A Dcx23885-417.c284 u32 regval; local
289 regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) |
292 cx_write(MC417_CTL, regval);
295 regval = MC417_MIRDY;
296 cx_write(MC417_OEN, regval);
299 regval = MC417_MIWR | MC417_MIRD | MC417_MICS;
300 cx_write(MC417_RWD, regval);
320 u32 regval; local
328 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 |
330 cx_write(MC417_RWD, regval);
385 u32 regval; local
478 u32 regval; local
543 u32 regval; local
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/drivers/rapidio/switches/
H A Dtsi57x.c124 u32 regval; local
132 TSI578_SP_MODE_GLBL, &regval);
134 regval & ~TSI578_SP_MODE_LUT_512);
146 u32 regval; local
152 TSI578_GLBL_ROUTE_BASE, &regval);
154 *sw_domain = (u8)(regval >> 24);
162 u32 regval; local
171 TSI578_SP_MODE(portnum), &regval);
174 regval & ~TSI578_SP_MODE_PW_DIS);
180 &regval);
221 u32 regval; local
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H A Didt_gen2.c203 u32 regval; local
209 IDT_RIO_DOMAIN, &regval);
211 *sw_domain = (u8)(regval & 0xff);
219 u32 regval; local
244 rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval);
246 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH);
262 rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval);
264 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW |
284 rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval);
286 regval | IDT_LANE_CTRL_GENP
328 u32 regval, em_perrdet, em_ltlerrdet; local
377 u32 regval; local
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/drivers/phy/
H A Dphy-berlin-sata.c69 u32 regval; local
75 regval = readl(ctrl_reg + PORT_VSR_DATA);
76 regval &= ~mask;
77 regval |= val;
78 writel(regval, ctrl_reg + PORT_VSR_DATA);
87 u32 regval; local
95 regval = readl(priv->base + HOST_VSA_DATA);
96 regval &= ~desc->power_bit;
97 writel(regval, priv->base + HOST_VSA_DATA);
101 regval
135 u32 regval; local
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/drivers/watchdog/
H A Dts72xx_wdt.c44 * @regval: watchdog timeout value suitable for control register
52 int regval; member in struct:ts72xx_wdt
88 int regval; member in struct:__anon7291
113 return ts72xx_wdt_map[i].regval;
121 * @regval: control register value to be converted
123 * Function converts given @regval to timeout in seconds (1, 2, 4 or 8).
124 * If @regval cannot be converted, function returns %-EINVAL.
126 static int regval_to_timeout(int regval) argument
131 if (ts72xx_wdt_map[i].regval == regval)
184 int regval; local
344 int regval; local
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/drivers/regulator/
H A Dtps6105x-regulator.c63 u8 regval; local
66 ret = tps6105x_get(tps6105x, TPS6105X_REG_0, &regval);
69 regval &= TPS6105X_REG0_MODE_MASK;
70 regval >>= TPS6105X_REG0_MODE_SHIFT;
72 if (regval == TPS6105X_REG0_MODE_VOLTAGE)
81 u8 regval; local
84 ret = tps6105x_get(tps6105x, TPS6105X_REG_0, &regval);
88 regval &= TPS6105X_REG0_VOLTAGE_MASK;
89 regval >>= TPS6105X_REG0_VOLTAGE_SHIFT;
90 return (int) regval;
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H A Dlp8755.c96 unsigned int regval; local
100 ret = lp8755_read(pchip, 0x12 + id, &regval);
105 return (regval & 0xff) * 100;
154 unsigned int regval; local
158 ret = lp8755_read(pchip, 0x06, &regval);
163 if (regval & (0x01 << id))
166 ret = lp8755_read(pchip, 0x08 + id, &regval);
171 if (regval & 0x20)
185 unsigned int regval = 0x00; local
192 regval
280 unsigned int regval; local
414 unsigned int regval; local
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H A Dab8500-ext.c63 u8 regval; local
75 regval = info->update_val_hp;
77 regval = info->update_val;
81 info->update_mask, regval);
91 info->update_mask, regval); local
100 u8 regval; local
111 regval = info->update_val_hw;
113 regval = 0;
117 info->update_mask, regval);
127 info->update_mask, regval); local
136 u8 regval; local
154 info->update_mask, regval); local
168 u8 regval; local
206 info->update_mask, regval); local
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H A Dab3100.c163 u8 regval; local
166 &regval);
174 if (regval & AB3100_REG_ON_MASK)
177 regval |= AB3100_REG_ON_MASK;
180 regval);
194 u8 regval; local
212 &regval);
218 regval &= ~AB3100_REG_ON_MASK;
220 regval);
226 u8 regval; local
243 u8 regval; local
277 u8 regval; local
306 u8 regval; local
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/drivers/mfd/
H A Dtps6105x.c69 u8 regval; local
77 regval = ret;
78 regval = (~bitmask & regval) | (bitmask & bitvalues);
79 ret = i2c_smbus_write_byte_data(tps6105x->client, reg, regval);
92 u8 regval; local
94 ret = tps6105x_get(tps6105x, TPS6105X_REG_0, &regval);
97 switch (regval >> TPS6105X_REG0_MODE_SHIFT) {
/drivers/net/ethernet/intel/i40e/
H A Di40e_ptp.c441 u32 pf_id, tsyntype, regval; local
511 regval = rd32(hw, I40E_PRTTSYN_CTL0);
513 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
515 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
516 wr32(hw, I40E_PRTTSYN_CTL0, regval);
518 regval = rd32(hw, I40E_PFINT_ICR0_ENA);
520 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
522 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
523 wr32(hw, I40E_PFINT_ICR0_ENA, regval);
529 regval
643 u32 regval; local
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/drivers/i2c/busses/
H A Di2c-sirf.c105 u32 regval; local
111 regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0);
114 regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK;
115 writel(regval,
124 regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0);
127 regval |= SIRFSOC_I2C_STOP;
128 writel(regval,
185 u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE; local
189 regval |= SIRFSOC_I2C_STOP;
191 writel(regval, sii
206 u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL); local
285 u32 regval; local
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/drivers/net/ethernet/intel/igb/
H A Digb_ptp.c470 u64 regval; local
472 regval = rd32(E1000_TXSTMPL);
473 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
475 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
496 __le64 *regval = (__le64 *)va; local
503 le64_to_cpu(regval[1]));
519 u64 regval; local
534 regval = rd32(E1000_RXSTMPL);
535 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
537 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
589 u32 regval; local
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/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c525 u32 regval; local
527 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
528 antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
530 antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
532 antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
542 u32 regval; local
544 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
545 regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
548 regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
550 regval |
564 u32 regval; local
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H A Dar9003_phy.c1414 u32 regval; local
1416 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1417 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1419 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1421 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1446 u32 regval; local
1448 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1449 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1454 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1456 regval |
1474 u32 regval; local
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/drivers/hwmon/
H A Dk10temp.c79 u32 regval; local
85 &regval);
87 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval);
89 return sprintf(buf, "%u\n", (regval >> 21) * 125);
103 u32 regval; local
107 REG_HARDWARE_THERMAL_CONTROL, &regval); local
108 value = ((regval >> 16) & 0x7f) * 500 + 52000;
110 value -= ((regval >> 24) & 0xf) * 500;
H A Dltc2945.c251 int regval; local
259 regval = ltc2945_val_to_reg(dev, reg, val);
261 regval = clamp_val(regval, 0, 0xffffff);
262 regbuf[0] = regval >> 16;
263 regbuf[1] = (regval >> 8) & 0xff;
264 regbuf[2] = regval;
267 regval = clamp_val(regval, 0, 0xfff) << 4;
268 regbuf[0] = regval >>
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H A Dltc4245.c177 const u8 regval = data->vregs[reg - 0x10]; local
183 voltage = regval * 55;
187 voltage = regval * 22;
191 voltage = regval * 15;
195 voltage = regval * -55;
198 voltage = regval * 10;
213 const u8 regval = data->vregs[reg - 0x10]; local
234 voltage = regval * 250; /* voltage in uV */
238 voltage = regval * 125; /* voltage in uV */
242 voltage = regval * 12
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/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_ptp.c476 u64 regval = 0, ns; local
479 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
480 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
483 ns = timecounter_cyc2time(&adapter->tc, regval);
541 u64 regval = 0, ns; local
549 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
550 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
553 ns = timecounter_cyc2time(&adapter->tc, regval);
606 u32 regval; local
676 regval
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/drivers/iio/adc/
H A Dtwl4030-madc.c679 u8 regval; local
682 &regval, TWL4030_BCI_BCICTL1);
691 regval |= regmask;
693 regval &= ~regmask;
696 regval, TWL4030_BCI_BCICTL1);
714 u8 regval; local
718 &regval, TWL4030_MADC_CTRL1);
725 regval |= TWL4030_MADC_MADCON;
727 regval &= ~TWL4030_MADC_MADCON;
728 ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, regval, TWL4030_MADC_CTRL
747 u8 regval; local
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H A Dad7291.c280 u16 regval; local
283 regval = chip->command;
301 regval &= ~AD7291_AUTOCYCLE;
302 regval |= chip->c_mask;
304 regval |= AD7291_AUTOCYCLE;
306 ret = ad7291_i2c_write(chip, AD7291_COMMAND, regval);
310 chip->command = regval;
329 u16 regval; local
342 regval = chip->command & (~AD7291_VOLTAGE_MASK);
343 regval |
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/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_core.c26 u32 regval; local
29 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG);
33 regval |= SXGBE_TX_JABBER_DISABLE;
34 writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG);
37 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG);
42 regval |= SXGBE_RX_JUMBPKT_ENABLE | SXGBE_RX_ACS_ENABLE;
43 writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
/drivers/rtc/
H A Drtc-ab3100.c205 u8 regval; local
210 AB3100_RTC, &regval);
216 if ((regval & 0xFE) != RTC_SETTING) {
218 regval);
221 if ((regval & 1) == 0) {
226 regval = 1 | RTC_SETTING;
228 AB3100_RTC, regval);
/drivers/staging/iio/cdc/
H A Dad7152.c98 u8 regval)
114 regval |= AD7152_CONF_CH1EN;
116 regval |= AD7152_CONF_CH2EN;
119 ret = i2c_smbus_write_byte_data(chip->client, AD7152_REG_CFG, regval);
132 } while ((ret == regval) && timeout--);
327 u8 regval = 0; local
335 regval = chip->setup[chan->channel];
342 if (regval != chip->setup[chan->channel]) {
351 regval = AD7152_CONF_CH1EN;
353 regval
94 ad7152_start_calib(struct device *dev, struct device_attribute *attr, const char *buf, size_t len, u8 regval) argument
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/drivers/video/fbdev/core/
H A Dsvgalib.c25 u8 regval, bitval, bitnum; local
28 regval = vga_rcrt(regbase, regset->regnum);
32 regval = regval & ~bitval;
33 if (value & 1) regval = regval | bitval;
37 vga_wcrt(regbase, regset->regnum, regval);
45 u8 regval, bitval, bitnum; local
48 regval = vga_rseq(regbase, regset->regnum);
52 regval
514 u8 regval; local
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