Searched refs:sq_config (Results 1 - 6 of 6) sorted by relevance

/drivers/gpu/drm/radeon/
H A Dr600_blit.c350 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; local
476 sq_config = 0;
478 sq_config = R600_VC_ENABLE;
480 sq_config |= (R600_DX9_CONSTS |
515 OUT_RING(sq_config);
H A Dr600_cp.c740 u32 sq_config; local
973 sq_config = RADEON_READ(R600_SQ_CONFIG);
974 sq_config &= ~(R600_PS_PRIO(3) |
978 sq_config |= (R600_DX9_CONSTS |
1004 sq_config &= ~R600_VC_ENABLE;
1050 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1367 u32 sq_config; local
1658 sq_config = RADEON_READ(R600_SQ_CONFIG);
1659 sq_config &= ~(R600_PS_PRIO(3) |
1663 sq_config |
[all...]
H A Drv770.c1174 u32 sq_config; local
1476 sq_config = RREG32(SQ_CONFIG);
1477 sq_config &= ~(PS_PRIO(3) |
1481 sq_config |= (DX9_CONSTS |
1490 sq_config &= ~VC_ENABLE;
1492 WREG32(SQ_CONFIG, sq_config);
H A Dr600_cs.c44 u32 sq_config; member in struct:r600_cs_track
304 track->sq_config = DX9_CONSTS;
1026 track->sq_config = radeon_get_ib_value(p, idx);
2024 if (track->sq_config & DX9_CONSTS) {
H A Dr600.c1910 u32 sq_config; local
2117 sq_config = RREG32(SQ_CONFIG);
2118 sq_config &= ~(PS_PRIO(3) |
2122 sq_config |= (DX9_CONSTS |
2148 sq_config &= ~VC_ENABLE;
2194 WREG32(SQ_CONFIG, sq_config);
H A Devergreen.c2999 u32 sq_config; local
3427 sq_config = RREG32(SQ_CONFIG);
3428 sq_config &= ~(PS_PRIO(3) |
3432 sq_config |= (VC_ENABLE |
3446 sq_config &= ~VC_ENABLE;
3488 WREG32(SQ_CONFIG, sq_config);

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