/drivers/gpu/drm/nouveau/core/engine/device/ |
H A D | ctrl.c | 40 struct nvif_control_pstate_info_v0 v0; member in union:__anon761 46 if (nvif_unpack(args->v0, 0, 0, false)) { 48 args->v0.version); 53 args->v0.count = clk->state_nr; 54 args->v0.ustate_ac = clk->ustate_ac; 55 args->v0.ustate_dc = clk->ustate_dc; 56 args->v0.pwrsrc = clk->pwrsrc; 57 args->v0.pstate = clk->pstate; 59 args->v0.count = 0; 60 args->v0 74 struct nvif_control_pstate_attr_v0 v0; member in union:__anon762 148 struct nvif_control_pstate_user_v0 v0; member in union:__anon763 [all...] |
H A D | base.c | 86 struct nv_device_info_v0 v0; member in union:__anon759 91 if (nvif_unpack(args->v0, 0, 0, false)) { 92 nv_ioctl(object, "device info vers %d\n", args->v0.version); 107 args->v0.platform = NV_DEVICE_INFO_V0_IGP; 112 args->v0.platform = NV_DEVICE_INFO_V0_AGP; 115 args->v0.platform = NV_DEVICE_INFO_V0_PCIE; 117 args->v0.platform = NV_DEVICE_INFO_V0_PCI; 119 args->v0.platform = NV_DEVICE_INFO_V0_SOC; 125 case NV_04: args->v0.family = NV_DEVICE_INFO_V0_TNT; break; 127 case NV_11: args->v0 281 struct nv_device_v0 v0; member in union:__anon760 [all...] |
/drivers/gpu/drm/nouveau/core/engine/disp/ |
H A D | dacnv50.c | 40 struct nv50_disp_dac_pwr_v0 v0; member in union:__anon766 46 if (nvif_unpack(args->v0, 0, 0, false)) { 49 args->v0.version, args->v0.state, args->v0.data, 50 args->v0.vsync, args->v0.hsync); 51 stat = 0x00000040 * !args->v0.state; 52 stat |= 0x00000010 * !args->v0.data; 53 stat |= 0x00000004 * !args->v0 68 struct nv50_disp_dac_load_v0 v0; member in union:__anon767 [all...] |
H A D | hdminvd0.c | 36 struct nv50_disp_sor_hdmi_pwr_v0 v0; member in union:__anon772 42 if (nvif_unpack(args->v0, 0, 0, false)) { 45 args->v0.version, args->v0.state, 46 args->v0.max_ac_packet, args->v0.rekey); 47 if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) 49 ctrl = 0x40000000 * !!args->v0.state; 50 ctrl |= args->v0 [all...] |
H A D | hdminve0.c | 37 struct nv50_disp_sor_hdmi_pwr_v0 v0; member in union:__anon773 43 if (nvif_unpack(args->v0, 0, 0, false)) { 46 args->v0.version, args->v0.state, 47 args->v0.max_ac_packet, args->v0.rekey); 48 if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) 50 ctrl = 0x40000000 * !!args->v0.state; 51 ctrl |= args->v0 [all...] |
H A D | sornv50.c | 39 struct nv50_disp_sor_pwr_v0 v0; member in union:__anon797 46 if (nvif_unpack(args->v0, 0, 0, false)) { 48 args->v0.version, args->v0.state); 49 stat = !!args->v0.state;
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H A D | hdminv84.c | 36 struct nv50_disp_sor_hdmi_pwr_v0 v0; member in union:__anon770 42 if (nvif_unpack(args->v0, 0, 0, false)) { 45 args->v0.version, args->v0.state, 46 args->v0.max_ac_packet, args->v0.rekey); 47 if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) 49 ctrl = 0x40000000 * !!args->v0.state; 50 ctrl |= args->v0 [all...] |
H A D | hdminva3.c | 36 struct nv50_disp_sor_hdmi_pwr_v0 v0; member in union:__anon771 42 if (nvif_unpack(args->v0, 0, 0, false)) { 45 args->v0.version, args->v0.state, 46 args->v0.max_ac_packet, args->v0.rekey); 47 if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) 49 ctrl = 0x40000000 * !!args->v0.state; 50 ctrl |= args->v0 [all...] |
H A D | nv04.c | 42 struct nv04_disp_scanoutpos_v0 v0; member in union:__anon774 48 if (nvif_unpack(args->v0, 0, 0, false)) { 49 nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version); 50 args->v0.vblanks = nv_rd32(priv, 0x680800 + hoff) & 0xffff; 51 args->v0.vtotal = nv_rd32(priv, 0x680804 + hoff) & 0xffff; 52 args->v0.vblanke = args->v0.vtotal - 1; 54 args->v0.hblanks = nv_rd32(priv, 0x680820 + hoff) & 0xffff; 55 args->v0.htotal = nv_rd32(priv, 0x680824 + hoff) & 0xffff; 56 args->v0 81 struct nv04_disp_mthd_v0 v0; member in union:__anon775 [all...] |
H A D | hdanva3.c | 37 struct nv50_disp_sor_hda_eld_v0 v0; member in union:__anon768 43 if (nvif_unpack(args->v0, 0, 0, true)) { 44 nv_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version); 50 if (size && args->v0.data[0]) { 56 nv_wr32(priv, 0x61c440 + soff, (i << 8) | args->v0.data[0]);
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H A D | hdanvd0.c | 37 struct nv50_disp_sor_hda_eld_v0 v0; member in union:__anon769 44 if (nvif_unpack(args->v0, 0, 0, true)) { 45 nv_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version); 51 if (size && args->v0.data[0]) { 58 nv_wr32(priv, 0x10ec00 + soff, (i << 8) | args->v0.data[i]);
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H A D | piornv50.c | 151 struct nv50_disp_pior_pwr_v0 v0; member in union:__anon796 157 if (nvif_unpack(args->v0, 0, 0, false)) { 159 args->v0.version, args->v0.state, args->v0.type); 160 if (args->v0.type > 0x0f) 162 ctrl = !!args->v0.state; 163 type = args->v0.type;
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H A D | base.c | 41 struct nvif_notify_head_req_v0 v0; member in union:__anon764 45 if (nvif_unpack(req->v0, 0, 0, false)) { 47 if (ret = -ENXIO, req->v0.head <= disp->vblank.index_nr) { 49 notify->index = req->v0.head; 71 struct nvif_notify_conn_req_v0 v0; member in union:__anon765 76 if (nvif_unpack(req->v0, 0, 0, false)) { 79 if (ret = -ENXIO, outp->conn->index == req->v0.conn) { 81 notify->types = req->v0.mask; 82 notify->index = req->v0.conn;
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/drivers/gpu/drm/nouveau/core/core/ |
H A D | ioctl.c | 59 struct nvif_ioctl_sclass_v0 v0; member in union:__anon745 69 if (nvif_unpack(args->v0, 0, 0, true)) { 71 args->v0.version, args->v0.count); 72 if (size == args->v0.count * sizeof(args->v0.oclass[0])) { 73 ret = nouveau_parent_lclass(object, args->v0.oclass, 74 args->v0.count); 76 args->v0.count = ret; 91 struct nvif_ioctl_new_v0 v0; member in union:__anon746 209 struct nvif_ioctl_mthd_v0 v0; member in union:__anon748 231 struct nvif_ioctl_rd_v0 v0; member in union:__anon749 273 struct nvif_ioctl_wr_v0 v0; member in union:__anon750 316 struct nvif_ioctl_map_v0 v0; member in union:__anon751 355 struct nvif_ioctl_ntfy_new_v0 v0; member in union:__anon753 384 struct nvif_ioctl_ntfy_del_v0 v0; member in union:__anon754 404 struct nvif_ioctl_ntfy_get_v0 v0; member in union:__anon755 424 struct nvif_ioctl_ntfy_put_v0 v0; member in union:__anon756 506 struct nvif_ioctl_v0 v0; member in union:__anon758 [all...] |
H A D | client.c | 43 struct nvif_notify_rep_v0 v0; member in union:nvkm_client_notify::__anon741 100 struct nvif_notify_req_v0 v0; member in union:__anon742 118 if (nvif_unpack(req->v0, 0, 0, true)) { 120 "token %llx\n", req->v0.version, 121 req->v0.reply, req->v0.route, req->v0.token); 122 notify->version = req->v0.version; 123 notify->size = sizeof(notify->rep.v0); 124 notify->rep.v0 148 struct nv_client_devlist_v0 v0; member in union:__anon743 [all...] |
/drivers/gpu/drm/nouveau/ |
H A D | nouveau_usif.c | 76 struct nvif_notify_rep_v0 v0; member in union:__anon911 82 if (length == sizeof(rep->v0) && rep->v0.version == 0) { 83 if (WARN_ON(!(ntfy = (void *)(unsigned long)rep->v0.token))) 85 BUG_ON(rep->v0.route != NVDRM_NOTIFY_USIF); 97 switch (rep->v0.version) { 126 struct nvif_ioctl_ntfy_new_v0 v0; member in union:__anon912 129 struct nvif_notify_req_v0 v0; member in union:__anon913 134 if (nvif_unpack(args->v0, 0, 0, true)) { 135 if (usif_notify_find(f, args->v0 170 struct nvif_ioctl_ntfy_del_v0 v0; member in union:__anon914 193 struct nvif_ioctl_ntfy_del_v0 v0; member in union:__anon915 232 struct nvif_ioctl_ntfy_put_v0 v0; member in union:__anon916 269 struct nvif_ioctl_new_v0 v0; member in union:__anon917 301 struct nvif_ioctl_v0 v0; member in union:__anon918 [all...] |
H A D | nouveau_nvif.c | 85 struct nvif_notify_req_v0 v0; member in union:__anon909 89 if (length == sizeof(args->v0) && args->v0.version == 0) { 90 route = args->v0.route;
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/drivers/gpu/drm/nouveau/core/engine/dmaobj/ |
H A D | base.c | 64 struct nv_dma_v0 v0; member in union:__anon798 81 if (nvif_unpack(args->v0, 0, 0, true)) { 84 args->v0.version, args->v0.target, args->v0.access, 85 args->v0.start, args->v0.limit); 86 dmaobj->target = args->v0.target; 87 dmaobj->access = args->v0.access; 88 dmaobj->start = args->v0 [all...] |
H A D | nv50.c | 93 struct nv50_dma_v0 v0; member in union:__anon799 106 if (nvif_unpack(args->v0, 0, 0, false)) { 108 "comp %d kind %02x\n", args->v0.version, 109 args->v0.priv, args->v0.part, args->v0.comp, 110 args->v0.kind); 111 user = args->v0.priv; 112 part = args->v0.part; 113 comp = args->v0 [all...] |
H A D | nvc0.c | 82 struct gf100_dma_v0 v0; member in union:__anon800 95 if (nvif_unpack(args->v0, 0, 0, false)) { 97 args->v0.version, args->v0.priv, args->v0.kind); 98 kind = args->v0.kind; 99 user = args->v0.priv;
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H A D | nvd0.c | 86 struct gf110_dma_v0 v0; member in union:__anon801 99 if (nvif_unpack(args->v0, 0, 0, false)) { 101 args->v0.version, args->v0.page, args->v0.kind); 102 kind = args->v0.kind; 103 page = args->v0.page;
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/drivers/gpu/drm/nouveau/core/engine/perfmon/ |
H A D | base.c | 110 struct nvif_perfctr_query_v0 v0; member in union:__anon828 122 if (nvif_unpack(args->v0, 0, 0, false)) { 124 args->v0.version, args->v0.iter); 125 di = (args->v0.iter & 0xff000000) >> 24; 126 si = (args->v0.iter & 0x00ffffff) - 1; 142 snprintf(args->v0.name, sizeof(args->v0.name), 145 strncpy(args->v0.name, name, sizeof(args->v0 222 struct nvif_perfctr_read_v0 v0; member in union:__anon830 274 struct nvif_perfctr_v0 v0; member in union:__anon831 [all...] |
/drivers/gpu/drm/nouveau/core/engine/fifo/ |
H A D | nv10.c | 64 struct nv03_channel_dma_v0 v0; member in union:__anon804 71 if (nvif_unpack(args->v0, 0, 0, false)) { 73 "offset %016llx\n", args->v0.version, 74 args->v0.pushbuf, args->v0.offset); 79 0x10000, args->v0.pushbuf, 87 args->v0.chid = chan->base.chid; 94 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); 95 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset);
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H A D | nv17.c | 69 struct nv03_channel_dma_v0 v0; member in union:__anon805 76 if (nvif_unpack(args->v0, 0, 0, false)) { 78 "offset %016llx\n", args->v0.version, 79 args->v0.pushbuf, args->v0.offset); 84 0x10000, args->v0.pushbuf, 94 args->v0.chid = chan->base.chid; 101 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); 102 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset);
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H A D | nv50.c | 199 struct nv03_channel_dma_v0 v0; member in union:__anon807 207 if (nvif_unpack(args->v0, 0, 0, false)) { 209 "offset %016llx\n", args->v0.version, 210 args->v0.pushbuf, args->v0.offset); 215 0x2000, args->v0.pushbuf, 224 args->v0.chid = chan->base.chid; 236 nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); 237 nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); 238 nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0 261 struct nv50_channel_gpfifo_v0 v0; member in union:__anon808 [all...] |