/drivers/phy/ |
H A D | phy-qcom-apq8064-sata.c | 104 writel_relaxed(0x01, base + SATA_PHY_SER_CTRL); 105 writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0); 110 writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); 111 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); 112 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); 113 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); 114 writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2); 117 writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG); 118 writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG); 120 writel_relaxed( [all...] |
H A D | phy-qcom-ipq806x-sata.c | 69 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); 76 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); 85 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); 90 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2); 95 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); 100 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); 111 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); 124 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
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/drivers/irqchip/ |
H A D | irq-gic-common.c | 49 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); 59 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); 62 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); 77 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, 84 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); 91 writel_relaxed(GICD_INT_EN_CLR_X32, 106 writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR); 107 writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); 113 writel_relaxed(GICD_INT_DEF_PRI_X4,
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H A D | irq-sirfsoc.c | 72 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); 73 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1); 75 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0); 76 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1); 109 writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); 110 writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); 111 writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0); 112 writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
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H A D | irq-hip04.c | 99 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR + 109 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET + 116 writel_relaxed(hip04_irq(d), hip04_cpu_base(d) + GIC_CPU_EOI); 162 writel_relaxed(val | bit, reg); 184 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 230 writel_relaxed(0, base + GIC_DIST_CTRL); 238 writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3)); 242 writel_relaxed(1, base + GIC_DIST_CTRL); 269 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); 270 writel_relaxed( [all...] |
/drivers/crypto/ux500/cryp/ |
H A D | cryp.c | 147 writel_relaxed(cr_for_kse, &device_data->base->cr); 218 writel_relaxed(key_value.key_value_left, 220 writel_relaxed(key_value.key_value_right, 224 writel_relaxed(key_value.key_value_left, 226 writel_relaxed(key_value.key_value_right, 230 writel_relaxed(key_value.key_value_left, 232 writel_relaxed(key_value.key_value_right, 236 writel_relaxed(key_value.key_value_left, 238 writel_relaxed(key_value.key_value_right, 265 writel_relaxed(init_vector_valu [all...] |
H A D | cryp_irq.c | 28 writel_relaxed(i, &device_data->base->imsc); 39 writel_relaxed(i, &device_data->base->imsc);
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H A D | cryp_p.h | 24 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name) 27 writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\ 34 writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \
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/drivers/mmc/host/ |
H A D | mmci_qcom_dml.c | 68 writel_relaxed(config, base + DML_CONFIG); 71 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); 74 writel_relaxed(data->blocks * data->blksz, 79 writel_relaxed(config, base + DML_CONFIG); 81 writel_relaxed(1, base + DML_PRODUCER_START); 88 writel_relaxed(config, base + DML_CONFIG); 92 writel_relaxed(config, base + DML_CONFIG); 94 writel_relaxed(1, base + DML_CONSUMER_START); 137 writel_relaxed(1, base + DML_SW_RESET); 158 writel_relaxed(confi [all...] |
/drivers/clocksource/ |
H A D | timer-marco.c | 59 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, 66 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3, 77 writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); 92 writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | 109 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 + 111 writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 + 147 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); 149 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], 151 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], 154 writel_relaxed(readl_relaxe [all...] |
H A D | timer-prima2.c | 68 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); 81 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, 95 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, 99 writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0); 100 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, 116 writel_relaxed(val | BIT(0), 120 writel_relaxed(val & ~BIT(0), 133 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, 147 writel_relaxed(sirfsoc_timer_reg_val[i], 150 writel_relaxed(sirfsoc_timer_reg_va [all...] |
H A D | time-efm32.c | 59 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); 60 writel_relaxed(ddata->periodic_top, ddata->base + TIMERn_TOP); 61 writel_relaxed(TIMERn_CTRL_PRESC_1024 | 65 writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); 69 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); 70 writel_relaxed(TIMERn_CTRL_PRESC_1024 | 79 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); 93 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); 94 writel_relaxed(evt, ddata->base + TIMERn_CNT); 95 writel_relaxed(TIMERn_CMD_STAR [all...] |
H A D | qcom-timer.c | 55 writel_relaxed(ctrl, event_base + TIMER_ENABLE); 67 writel_relaxed(ctrl, event_base + TIMER_ENABLE); 69 writel_relaxed(ctrl, event_base + TIMER_CLEAR); 70 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); 76 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); 99 writel_relaxed(ctrl, event_base + TIMER_ENABLE); 226 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE); 282 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
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/drivers/video/fbdev/mmp/hw/ |
H A D | mmp_ctrl.c | 55 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); 139 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); 152 writel_relaxed(win->pitch[0], ®s->v_pitch_yc); 153 writel_relaxed(win->pitch[2] << 16 | 156 writel_relaxed((win->ysrc << 16) | win->xsrc, ®s->v_size); 157 writel_relaxed((win->ydst << 16) | win->xdst, ®s->v_size_z); 158 writel_relaxed(win->ypos << 16 | win->xpos, ®s->v_start); 160 writel_relaxed(win->pitch[0], ®s->g_pitch); 162 writel_relaxed((win->ysrc << 16) | win->xsrc, ®s->g_size); 163 writel_relaxed((wi [all...] |
H A D | mmp_spi.c | 51 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); 55 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); 58 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); 61 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); 87 writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL); 89 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); 113 writel_relaxed(IOPAD_DUMB18SPI |
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/drivers/clk/mxs/ |
H A D | clk-pll.c | 43 writel_relaxed(1 << pll->power, pll->base + SET); 54 writel_relaxed(1 << pll->power, pll->base + CLR); 61 writel_relaxed(1 << 31, pll->base + CLR); 70 writel_relaxed(1 << 31, pll->base + SET);
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/drivers/spi/ |
H A D | spi-qup.c | 181 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); 182 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); 186 writel_relaxed(cur_state, controller->base + QUP_STATE); 265 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); 286 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); 287 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); 288 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); 372 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); 373 writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); 375 writel_relaxed( [all...] |
/drivers/mfd/ |
H A D | mcp-sa11x0.c | 56 writel_relaxed(m->mccr0, MCCR0(m)); 68 writel_relaxed(m->mccr0, MCCR0(m)); 84 writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m)); 111 writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m)); 133 writel_relaxed(m->mccr0, MCCR0(m)); 141 writel_relaxed(m->mccr0, MCCR0(m)); 211 writel_relaxed(-1, MCSR(m)); 212 writel_relaxed(m->mccr1, MCCR1(m)); 213 writel_relaxed(m->mccr0, MCCR0(m)); 279 writel_relaxed( [all...] |
/drivers/watchdog/ |
H A D | sa1100_wdt.c | 57 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); 58 writel_relaxed(OSSR_M3, OSSR); 59 writel_relaxed(OWER_WME, OWER); 60 writel_relaxed(readl_relaxed(OIER) | OIER_E3, OIER); 83 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); 117 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); 132 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
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H A D | sp805_wdt.c | 140 writel_relaxed(UNLOCK, wdt->base + WDTLOCK); 141 writel_relaxed(wdt->load_val, wdt->base + WDTLOAD); 144 writel_relaxed(INT_MASK, wdt->base + WDTINTCLR); 145 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + 149 writel_relaxed(LOCK, wdt->base + WDTLOCK); 176 writel_relaxed(UNLOCK, wdt->base + WDTLOCK); 177 writel_relaxed(0, wdt->base + WDTCONTROL); 178 writel_relaxed(LOCK, wdt->base + WDTLOCK);
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/drivers/net/ethernet/hisilicon/ |
H A D | hix5hd2_gmac.c | 265 writel_relaxed(val, priv->ctrl_base); 267 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); 274 writel_relaxed(val, priv->base + PORT_MODE); 275 writel_relaxed(0, priv->base + MODE_CHANGE_EN); 276 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); 281 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); 282 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); 283 writel_relaxed(0, priv->base + RX_FQ_REG_EN); 285 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); 286 writel_relaxed(r [all...] |
/drivers/media/rc/ |
H A D | ir-hix5hd2.c | 20 #ifndef writel_relaxed 21 # define writel_relaxed writel macro 102 writel_relaxed(0x01, priv->base + IR_ENABLE); 120 writel_relaxed(val, priv->base + IR_CONFIG); 122 writel_relaxed(0x00, priv->base + IR_INTM); 124 writel_relaxed(0x01, priv->base + IR_START); 162 writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC); 191 writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC); 193 writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC); 318 writel_relaxed( [all...] |
/drivers/gpio/ |
H A D | gpio-mvebu.c | 196 writel_relaxed(u, mvebu_gpioreg_out(mvchip)); 229 writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); 250 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 277 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 300 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip)); 312 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); 324 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); 336 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); 348 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); 410 writel_relaxed( [all...] |
H A D | gpio-pxa.c | 236 writel_relaxed(value, base + GPDR_OFFSET); 249 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 258 writel_relaxed(tmp, base + GPDR_OFFSET); 272 writel_relaxed(1 << offset, gpio_chip_base(chip) + 346 writel_relaxed(grer, c->regbase + GRER_OFFSET); 347 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 374 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); 376 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); 412 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); 430 writel_relaxed(GPIO_bi [all...] |
/drivers/clk/tegra/ |
H A D | clk-periph-gate.c | 34 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg)) 36 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg)) 41 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg)) 88 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); 89 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); 91 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
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