Searched refs:x2 (Results 1 - 25 of 186) sorted by relevance

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/include/linux/ceph/
H A Dceph_hash.h5 #define CEPH_STR_HASH_RJENKINS 0x2 /* robert jenkins' */
/include/linux/platform_data/
H A Dad5449.h25 AD5449_SDO_OPEN_DRAIN = 0x2,
H A Dadau1977.h28 ADAU1977_MICBIAS_6V0 = 0x2,
H A Dasoc-ti-mcbsp.h28 #define MCBSP_CONFIG_TYPE2 0x2
/include/uapi/linux/
H A Dif_plip.h25 #define PLIP_SET_TIMEOUT 0x2
H A Dcoda_psdev.h23 #define CODA_REQ_READ 0x2
H A Dfirewire-constants.h31 #define TCODE_WRITE_RESPONSE 0x2
42 #define EXTCODE_COMPARE_SWAP 0x2
73 #define SCODE_400 0x2
80 #define ACK_PENDING 0x2
H A Dvirtio_pci.h71 #define VIRTIO_PCI_ISR_CONFIG 0x2
H A Disdn_ppp.h17 #define CALLTYPE_OUTGOING 0x2
58 #define IPPP_COMP_FLAG_LINK 0x2
H A Dif_vlan.h35 VLAN_FLAG_GVRP = 0x2,
/include/drm/
H A Ddrm_rect.h37 * @x2: horizontal ending coordinate (exclusive)
42 int x1, y1, x2, y2; member in struct:drm_rect
61 r->x2 += (dw + 1) >> 1;
78 r->x2 += dx;
94 r->x2 /= horz;
107 return r->x2 - r->x1;
145 return r1->x1 == r2->x1 && r1->x2 == r2->x2 &&
/include/linux/mfd/wm8350/
H A Dgpio.h41 #define WM8350_GPIO0_LDO_EN_IN 0x2
42 #define WM8350_GPIO0_VRTC_OUT 0x2
50 #define WM8350_GPIO1_LDO_EN_IN 0x2
51 #define WM8350_GPIO1_RESET_OUT 0x2
59 #define WM8350_GPIO2_WAKE_UP_IN 0x2
60 #define WM8350_GPIO2_VRTC_OUT 0x2
68 #define WM8350_GPIO3_LDO_EN_IN 0x2
69 #define WM8350_GPIO3_VRTC_OUT 0x2
77 #define WM8350_GPIO4_FLASH_IN 0x2
78 #define WM8350_GPIO4_ADA_OUT 0x2
[all...]
/include/dt-bindings/dma/
H A Dat91.h25 #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */
/include/linux/i2c/
H A Dapds990x.h30 #define APDS_IRLED_CURR_25mA 0x2
/include/uapi/linux/netfilter/
H A Dxt_devgroup.h8 XT_DEVGROUP_INVERT_SRC = 0x2,
/include/uapi/linux/tc_act/
H A Dtc_skbedit.h28 #define SKBEDIT_F_QUEUE_MAPPING 0x2
/include/video/
H A Diga.h19 #define MEM_SIZE_4M 0x2
H A Dsamsung_fimd.h28 #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
38 #define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
47 #define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
56 #define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
85 #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
106 #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
199 #define WINCONx_BURSTLEN_4WORD (0x2 << 9)
206 #define WINCON0_BPPMODE_4BPP (0x2 << 2)
219 #define WINCON1_BPPMODE_4BPP (0x2 << 2)
327 #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 1
[all...]
/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h32 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (0x2 << 30)
37 #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (0x2 << 28)
41 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (0x2 << 26)
51 #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (0x2 << 22)
56 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20)
61 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18)
66 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16)
71 #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (0x2 << 14)
129 #define IMX6Q_GPR1_ADDRS3_128MB (0x2 << 10)
141 #define IMX6Q_GPR2_COUNTER_RESET_VAL_4 (0x2 << 2
[all...]
/include/dt-bindings/pinctrl/
H A Dat91.h25 #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
/include/linux/
H A Dintel_mid_dma.h49 LNW_DMA_MSIZE_8 = 0x2,
H A Djz4740-adc.h22 #define JZ_ADC_CONFIG_XYZ_MASK (0x2 << 13)
H A Dleds-lp3944.h29 LP3944_LED_STATUS_DIM0 = 0x2,
H A Dsxgbe_platform.h19 #define SXGBE_CSR_250_300M 0x2 /* MDC = clk_scr_i/122 */
/include/net/
H A Daf_ieee802154.h32 IEEE802154_ADDR_SHORT = 0x2, /* 16-bit address + PANid */

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