Searched refs:MHz (Results 1 - 10 of 10) sorted by relevance

/drivers/ata/
H A Dpata_hpt37x.c822 static const int MHz[4] = { 33, 40, 50, 66 }; local
979 * use a 50MHz DPLL by choice
987 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
1021 MHz[clock_slot], MHz[dpll]);
1036 chip_table->name, MHz[clock_slot]);
/drivers/gpu/drm/gma500/
H A Dpsb_device.c47 #define MHz 1000000 macro
88 value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
H A Doaktrail_device.c58 #define MHz 1000000 macro
126 value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
H A Dmdfld_device.c33 #define MHz 1000000 macro
/drivers/video/fbdev/
H A Dimsttfb.c135 * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1)
438 setclkMHz(struct imstt_par *par, __u32 MHz) argument
454 if (x == MHz)
456 if (x > MHz) {
459 } else if (spilled && x < MHz) {
473 __u32 MHz, hes, heb, veb, htp, vtp; local
478 MHz = 30 /* .25 */ ;
482 MHz = 57 /* .27_ */ ;
486 MHz = 80;
490 MHz
[all...]
/drivers/clk/pxa/
H A Dclk-pxa27x.c24 #define MHz (1000 * 1000) macro
212 13 * MHz);
/drivers/media/tuners/
H A Dmxl5007t.c66 #define MHz 1000000 macro
435 * 10 bit integer (MHz) + 6 bit fraction */
436 dig_rf_freq = rf_freq / MHz;
438 temp = rf_freq % MHz;
/drivers/gpu/drm/i915/
H A Dintel_drv.h73 #define MHz(x) KHz(1000 * (x)) macro
H A Dintel_display.c135 static inline u32 /* units of 100MHz */
765 /* min update 19.2 MHz */
3514 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3520 /* The iCLK virtual clock root frequency is in MHz,
4583 * BSpec erroneously claims we should aim for 4MHz, but
4584 * in fact 1MHz is the correct frequency.
4597 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4708 * 200MHz
4709 * 267MHz
4710 * 320/333MHz (depend
[all...]
/drivers/watchdog/
H A DKconfig242 signal, so with reasonably fast systems (PCLK around 50-66MHz)

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