| /drivers/gpu/drm/nouveau/core/subdev/clock/ |
| H A D | pll.h | 5 int *N1, int *M1, int *N2, int *M2, int *P);
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| H A D | pllnv04.c | 152 int M1, N1, M2, N2, log2P; local
185 N2 = (clkP * M2 + calcclk1/2) / calcclk1;
186 if (N2 < minN2)
188 if (N2 > maxN2)
193 if (N2/M2 < 4 || N2/M2 > 10)
196 calcclk2 = calcclk1 * N2 / M2;
214 *pN2 = N2;
229 int *N1, int *M1, int *N2, int *M2, int *P)
233 if (!info->vco2.max_freq || !N2) {
228 nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq, int *N1, int *M1, int *N2, int *M2, int *P) argument
[all...] |
| H A D | nv04.c | 40 int N1, M1, N2, M2, P; local
41 int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
46 pv->N2 = N2;
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| H A D | nv40.c | 69 int N2 = (coef & 0xff000000) >> 24; local
80 clk = clk * N2 / M2;
131 int *N1, int *M1, int *N2, int *M2, int *log2P)
144 ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P);
156 int N1, M1, N2, M2, log2P; local
161 &N1, &M1, &N2, &M2, &log2P);
165 if (N2 == M2) {
170 priv->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
130 nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P) argument
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| H A D | nv50.c | 162 int N1, N2, M1, M2; local
170 N2 = (coef & 0xff000000) >> 24;
178 freq = freq * N2 / M2;
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| /drivers/gpu/drm/nouveau/core/include/subdev/bios/ |
| H A D | pll.h | 9 uint8_t N1, M1, N2, M2; member in struct:nouveau_pll_vals::__anon845::__anon846
11 uint8_t M1, N1, M2, N2;
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| /drivers/gpu/drm/nouveau/core/subdev/devinit/ |
| H A D | nv50.c | 39 int N1, M1, N2, M2, P; local
48 ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, &N1, &M1, &N2, &M2, &P);
60 (M2 << 16) | N2);
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| H A D | nv04.c | 204 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
210 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
211 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
290 bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
356 int N1, M1, N2, M2, P; local
364 &N1, &M1, &N2, &M2, &P);
371 pv.N2 = N2;
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| /drivers/gpu/drm/nouveau/core/subdev/fb/ |
| H A D | ramnv40.c | 43 int N1, M1, N2, M2; local
53 &N1, &M1, &N2, &M2, &log2P);
59 if (N2 == M2) {
64 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
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| H A D | ramnv50.c | 78 int N1, M1, N2, M2, P; local
139 &N1, &M1, &N2, &M2, &P);
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| H A D | ramnve0.c | 140 int N2, M2, P2; member in struct:nve0_ram
166 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
1001 &ram->N2, NULL, &ram->M2, &ram->P2);
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| /drivers/cpufreq/ |
| H A D | pxa2xx-cpufreq.c | 149 #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| H A D | hw.c | 141 pllvals->N2 = pllvals->M2 = 1;
156 pllvals->N2 = ((pll1 >> 21) & 0x18) |
211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
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| H A D | crtc.c | 159 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
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| /drivers/net/wan/ |
| H A D | Kconfig | 219 config N2
220 tristate "SDL RISCom/N2 support"
223 Driver for RISCom/N2 single or dual channel ISA cards by
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| /drivers/tty/ |
| H A D | n_gsm.c | 73 #define N2 3 /* Retry 3 times */ macro
2185 gsm->n2 = N2;
2541 /* This will timeout if the link is down due to N2 expiring */
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| /drivers/net/wireless/brcm80211/brcmsmac/phy/ |
| H A D | phy_lcn.c | 2071 u16 N1, N2, N3, N4, N5, N6, N; local
2074 N2 = 1 << ((read_phy_reg(pi, 0x4a5) & (0x7 << 12))
2084 N = 2 * (N1 + N2 + N3 + N4 + 2 * (N5 + N6)) + 80;
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