/drivers/watchdog/ |
H A D | it8712f_wdt.c | 62 #define VAL 0x2f /* The value to read/write */ macro 100 return inb(VAL); 106 outb(val, VAL); 113 val = inb(VAL) << 8; 115 val |= inb(VAL); 122 outb(ldn, VAL); 143 outb(0x02, VAL);
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H A D | it87_wdt.c | 65 #define VAL 0x2f macro 191 outb(0x02, VAL); 198 outb(ldn, VAL); 204 return inb(VAL); 210 outb(val, VAL); 217 val = inb(VAL) << 8; 219 val |= inb(VAL); 226 outb(val >> 8, VAL); 228 outb(val, VAL);
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/drivers/net/ethernet/qlogic/qlcnic/ |
H A D | qlcnic_hdr.h | 642 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) 643 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) 644 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) 645 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) 646 #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) [all...] |
H A D | qlcnic_83xx_hw.h | 405 #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2))) 406 #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2))
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H A D | qlcnic.h | 876 #define QLCNIC_IS_LB_CONFIGURED(VAL) \ 877 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
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/drivers/rtc/ |
H A D | rtc-at32ap700x.c | 75 now = rtc_readl(rtc, VAL); 89 rtc_writel(rtc, VAL, now); 114 rtc_unix_time = rtc_readl(rtc, VAL); 145 if (rtc_readl(rtc, VAL) > rtc->alarm_time) { 179 rtc_writel(rtc, VAL, rtc->alarm_time); 233 * Do not reset VAL register, as it can hold an old time
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/drivers/net/ethernet/qlogic/netxen/ |
H A D | netxen_nic_hdr.h | 966 #define NETXEN_DIMM_MEMTYPE(VAL) ((VAL >> 3) & 0xf) 967 #define NETXEN_DIMM_NUMROWS(VAL) ((VAL >> 7) & 0xf) 968 #define NETXEN_DIMM_NUMCOLS(VAL) ((VAL >> 11) & 0xf) 969 #define NETXEN_DIMM_NUMRANKS(VAL) ((VAL >> 15) & 0x3) 970 #define NETXEN_DIMM_DATAWIDTH(VAL) ((VAL >> 1 [all...] |
/drivers/scsi/ |
H A D | sun3x_esp.c | 44 #define dma_write32(VAL, REG) \ 45 writel((VAL), esp->dma_regs + (REG)) 49 #define dma_write32(VAL, REG) \ 50 do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
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H A D | aha152x.h | 288 #define SETPORT(PORT, VAL) outb( (VAL), (PORT) )
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H A D | mac_esp.c | 49 #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG)
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H A D | sun_esp.c | 32 #define dma_write32(VAL, REG) \ 33 sbus_writel((VAL), esp->dma_regs + (REG))
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H A D | esp_scsi.c | 104 #define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG)
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/drivers/staging/comedi/drivers/ |
H A D | s626.h | 366 #define S626_I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) 367 #define S626_I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) 368 #define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
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/drivers/hwmon/ |
H A D | smsc47b397.c | 55 #define VAL 0x2f /* The value to read/write */ macro 60 outb(val, VAL); 66 return inb(VAL);
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H A D | smsc47m1.c | 57 #define VAL 0x2f /* The value to read/write */ macro 63 outb(val, VAL); 70 return inb(VAL);
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H A D | it87.c | 79 #define VAL 0x2f /* The value to read/write */ macro 91 return inb(VAL); 97 outb(val, VAL); 104 val = inb(VAL) << 8; 106 val |= inb(VAL); 113 outb(ldn, VAL); 134 outb(0x02, VAL);
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/drivers/net/ethernet/freescale/fs_enet/ |
H A D | mii-fec.c | 47 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
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H A D | mac-fcc.c | 74 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
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/drivers/scsi/qla2xxx/ |
H A D | qla_nx.h | 703 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) 704 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
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/drivers/scsi/qla4xxx/ |
H A D | ql4_nx.h | 764 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) 765 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
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/drivers/block/ |
H A D | skd_main.c | 356 #define SKD_WRITEL(DEV, VAL, OFF) skd_reg_write32(DEV, VAL, OFF) 358 #define SKD_WRITEQ(DEV, VAL, OFF) skd_reg_write64(DEV, VAL, OFF)
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