/drivers/gpu/drm/nouveau/core/subdev/fb/ |
H A D | nv84.c | 29 .base.base.handle = NV_SUBDEV(FB, 0x84), 30 .base.base.ofuncs = &(struct nouveau_ofuncs) { 36 .base.memtype = nv50_fb_memtype_valid, 37 .base.ram = &nv50_ram_oclass, 39 }.base.base;
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H A D | nva3.c | 29 .base.base.handle = NV_SUBDEV(FB, 0xa3), 30 .base.base.ofuncs = &(struct nouveau_ofuncs) { 36 .base.memtype = nv50_fb_memtype_valid, 37 .base.ram = &nva3_ram_oclass, 39 }.base.base;
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H A D | nvaa.c | 29 .base.base.handle = NV_SUBDEV(FB, 0xaa), 30 .base.base.ofuncs = &(struct nouveau_ofuncs) { 36 .base.memtype = nv50_fb_memtype_valid, 37 .base.ram = &nvaa_ram_oclass, 39 }.base.base;
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H A D | nvaf.c | 29 .base.base.handle = NV_SUBDEV(FB, 0xaf), 30 .base.base.ofuncs = &(struct nouveau_ofuncs) { 36 .base.memtype = nv50_fb_memtype_valid, 37 .base.ram = &nvaa_ram_oclass, 39 }.base.base;
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H A D | nv1a.c | 31 .base.base.handle = NV_SUBDEV(FB, 0x1a), 32 .base.base.ofuncs = &(struct nouveau_ofuncs) { 38 .base.memtype = nv04_fb_memtype_valid, 39 .base.ram = &nv1a_ram_oclass, 44 }.base.base;
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H A D | nv4e.c | 31 .base.base.handle = NV_SUBDEV(FB, 0x4e), 32 .base.base.ofuncs = &(struct nouveau_ofuncs) { 38 .base.memtype = nv04_fb_memtype_valid, 39 .base.ram = &nv4e_ram_oclass, 44 }.base.base;
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H A D | nv47.c | 31 .base.base.handle = NV_SUBDEV(FB, 0x47), 32 .base.base.ofuncs = &(struct nouveau_ofuncs) { 38 .base.memtype = nv04_fb_memtype_valid, 39 .base.ram = &nv41_ram_oclass, 45 }.base.base;
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H A D | nv49.c | 31 .base.base.handle = NV_SUBDEV(FB, 0x49), 32 .base.base.ofuncs = &(struct nouveau_ofuncs) { 38 .base.memtype = nv04_fb_memtype_valid, 39 .base.ram = &nv49_ram_oclass, 45 }.base.base;
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H A D | nv04.c | 44 ret = nouveau_fb_init(&priv->base); 70 priv->base.tile.regions = impl->tile.regions; 71 priv->base.tile.init = impl->tile.init; 72 priv->base.tile.comp = impl->tile.comp; 73 priv->base.tile.fini = impl->tile.fini; 74 priv->base.tile.prog = impl->tile.prog; 80 .base.base.handle = NV_SUBDEV(FB, 0x04), 81 .base.base [all...] |
H A D | nv46.c | 45 .base.base.handle = NV_SUBDEV(FB, 0x46), 46 .base.base.ofuncs = &(struct nouveau_ofuncs) { 52 .base.memtype = nv04_fb_memtype_valid, 53 .base.ram = &nv44_ram_oclass, 58 }.base.base;
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/drivers/media/platform/s5p-jpeg/ |
H A D | jpeg-hw-exynos4.h | 16 void exynos4_jpeg_sw_reset(void __iomem *base); 17 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode); 18 void exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt); 19 void exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt); 20 void exynos4_jpeg_set_enc_tbl(void __iomem *base); 21 void exynos4_jpeg_set_interrupt(void __iomem *base); 22 unsigned int exynos4_jpeg_get_int_status(void __iomem *base); 23 void exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value); 24 void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value); 25 void exynos4_jpeg_set_stream_buf_address(void __iomem *base, [all...] |
H A D | jpeg-hw-exynos4.c | 19 void exynos4_jpeg_sw_reset(void __iomem *base) argument 23 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); 24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); 28 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); 31 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) argument 35 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); 40 base + EXYNOS4_JPEG_CNTL_REG); 44 base + EXYNOS4_JPEG_CNTL_REG); 48 void exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt) argument 52 reg = readl(base 121 exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt) argument 152 exynos4_jpeg_set_interrupt(void __iomem *base) argument 157 exynos4_jpeg_get_int_status(void __iomem *base) argument 166 exynos4_jpeg_get_fifo_status(void __iomem *base) argument 175 exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value) argument 189 exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value) argument 201 exynos4_jpeg_set_stream_buf_address(void __iomem *base, unsigned int address) argument 207 exynos4_jpeg_set_stream_size(void __iomem *base, unsigned int x_value, unsigned int y_value) argument 215 exynos4_jpeg_set_frame_buf_address(void __iomem *base, struct s5p_jpeg_addr *exynos4_jpeg_addr) argument 223 exynos4_jpeg_set_encode_tbl_select(void __iomem *base, enum exynos4_jpeg_img_quality_level level) argument 237 exynos4_jpeg_set_encode_hoff_cnt(void __iomem *base, unsigned int fmt) argument 245 exynos4_jpeg_get_stream_size(void __iomem *base) argument 253 exynos4_jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size) argument 258 exynos4_jpeg_get_frame_size(void __iomem *base, unsigned int *width, unsigned int *height) argument 267 exynos4_jpeg_get_frame_fmt(void __iomem *base) argument 273 exynos4_jpeg_set_timer_count(void __iomem *base, unsigned int size) argument [all...] |
/drivers/watchdog/ |
H A D | nv_tco.h | 34 #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */ 35 #define TCO_TMR(base) ((base) + 0x01) /* TCO Timer Initial Value */ 37 #define TCO_STS(base) ((base) + 0x04) /* TCO Status Register */ 53 #define TCO_CNT(base) ((base) + 0x08) /* TCO Control Register */ 60 * The SMI_EN register is at the base io address + 0x04, 63 #define MCP51_SMI_EN(base) ((bas [all...] |
/drivers/scsi/ |
H A D | nsp32_io.h | 12 static inline void nsp32_write1(unsigned int base, argument 16 outb(val, (base + index)); 19 static inline unsigned char nsp32_read1(unsigned int base, argument 22 return inb(base + index); 25 static inline void nsp32_write2(unsigned int base, argument 29 outw(val, (base + index)); 32 static inline unsigned short nsp32_read2(unsigned int base, argument 35 return inw(base + index); 38 static inline void nsp32_write4(unsigned int base, argument 42 outl(val, (base 45 nsp32_read4(unsigned int base, unsigned int index) argument 53 nsp32_mmio_write1(unsigned long base, unsigned int index, unsigned char val) argument 64 nsp32_mmio_read1(unsigned long base, unsigned int index) argument 74 nsp32_mmio_write2(unsigned long base, unsigned int index, unsigned short val) argument 85 nsp32_mmio_read2(unsigned long base, unsigned int index) argument 95 nsp32_mmio_write4(unsigned long base, unsigned int index, unsigned long val) argument 106 nsp32_mmio_read4(unsigned long base, unsigned int index) argument 118 nsp32_index_read1(unsigned int base, unsigned int reg) argument 125 nsp32_index_write1(unsigned int base, unsigned int reg, unsigned char val) argument 133 nsp32_index_read2(unsigned int base, unsigned int reg) argument 140 nsp32_index_write2(unsigned int base, unsigned int reg, unsigned short val) argument 148 nsp32_index_read4(unsigned int base, unsigned int reg) argument 160 nsp32_index_write4(unsigned int base, unsigned int reg, unsigned long val) argument 176 nsp32_mmio_index_read1(unsigned long base, unsigned int reg) argument 188 nsp32_mmio_index_write1(unsigned long base, unsigned int reg, unsigned char val) argument 201 nsp32_mmio_index_read2(unsigned long base, unsigned int reg) argument 213 nsp32_mmio_index_write2(unsigned long base, unsigned int reg, unsigned short val) argument 228 nsp32_multi_read4(unsigned int base, unsigned int reg, void *buf, unsigned long count) argument 236 nsp32_fifo_read(unsigned int base, void *buf, unsigned long count) argument 243 nsp32_multi_write4(unsigned int base, unsigned int reg, void *buf, unsigned long count) argument 251 nsp32_fifo_write(unsigned int base, void *buf, unsigned long count) argument [all...] |
H A D | aha1740.h | 18 #define HID0(base) (base + 0x0) 19 #define HID1(base) (base + 0x1) 20 #define HID2(base) (base + 0x2) 21 #define HID3(base) (base + 0x3) 22 #define EBCNTRL(base) (base [all...] |
/drivers/gpu/drm/nouveau/core/engine/mpeg/ |
H A D | nv31.h | 7 struct nouveau_object base; member in struct:nv31_mpeg_chan 11 struct nouveau_mpeg base; member in struct:nv31_mpeg_priv
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/drivers/gpu/drm/nouveau/core/engine/perfmon/ |
H A D | nvc0.h | 7 struct nouveau_perfmon base; member in struct:nvc0_perfmon_priv 11 struct nouveau_perfctr base; member in struct:nvc0_perfmon_cntr
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/drivers/gpu/drm/nouveau/core/subdev/therm/ |
H A D | nva3.c | 30 struct nouveau_therm_priv base; member in struct:nva3_therm_priv 47 struct dcb_gpio_func *tach = &priv->base.fan->tach; 50 ret = nouveau_therm_init(&priv->base.base); 54 nv84_sensor_setup(&priv->base.base); 82 priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl; 83 priv->base.base [all...] |
/drivers/scsi/pcmcia/ |
H A D | nsp_io.h | 15 static inline void nsp_write(unsigned int base, 18 static inline unsigned char nsp_read(unsigned int base, 30 static inline void nsp_write(unsigned int base, argument 34 outb(val, (base + index)); 37 static inline unsigned char nsp_read(unsigned int base, argument 40 return inb(base + index); 75 static inline void nsp_fifo8_read(unsigned int base, argument 80 nsp_multi_read_1(base, FIFODATA, buf, count); 94 static inline void nsp_fifo16_read(unsigned int base, argument 99 nsp_multi_read_2(base, FIFODAT 113 nsp_fifo32_read(unsigned int base, void *buf, unsigned long count) argument 132 nsp_fifo8_write(unsigned int base, void *buf, unsigned long count) argument 150 nsp_fifo16_write(unsigned int base, void *buf, unsigned long count) argument 168 nsp_fifo32_write(unsigned int base, void *buf, unsigned long count) argument 178 nsp_mmio_write(unsigned long base, unsigned int index, unsigned char val) argument 187 nsp_mmio_read(unsigned long base, unsigned int index) argument 197 nsp_mmio_index_read(unsigned long base, unsigned int reg) argument 207 nsp_mmio_index_write(unsigned long base, unsigned int reg, unsigned char val) argument 219 nsp_mmio_multi_read_4(unsigned long base, unsigned int Register, void *buf, unsigned long count) argument 237 nsp_mmio_fifo32_read(unsigned int base, void *buf, unsigned long count) argument 245 nsp_mmio_multi_write_4(unsigned long base, unsigned int Register, void *buf, unsigned long count) argument 263 nsp_mmio_fifo32_write(unsigned int base, void *buf, unsigned long count) argument [all...] |
/drivers/isdn/hardware/avm/ |
H A D | avmcard.h | 219 static inline unsigned char b1outp(unsigned int base, argument 223 outb(value, base + offset); 224 return inb(base + B1_ANALYSE); 228 static inline int b1_rx_full(unsigned int base) argument 230 return inb(base + B1_INSTAT) & 0x1; 233 static inline unsigned char b1_get_byte(unsigned int base) argument 236 while (!b1_rx_full(base) && time_before(jiffies, stop)); 237 if (b1_rx_full(base)) 238 return inb(base + B1_READ); 239 printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base); 243 b1_get_word(unsigned int base) argument 253 b1_tx_empty(unsigned int base) argument 258 b1_put_byte(unsigned int base, unsigned char val) argument 264 b1_save_put_byte(unsigned int base, unsigned char val) argument 273 b1_put_word(unsigned int base, unsigned int val) argument 281 b1_get_slice(unsigned int base, unsigned char *dp) argument 291 b1_put_slice(unsigned int base, unsigned char *dp, unsigned int len) argument 300 b1_wr_reg(unsigned int base, unsigned int reg, unsigned int value) argument 309 b1_rd_reg(unsigned int base, unsigned int reg) argument 318 b1_reset(unsigned int base) argument 330 b1_disable_irq(unsigned int base) argument 337 b1_set_test_bit(unsigned int base, enum avmcardtype cardtype, int onoff) argument 344 b1_get_test_bit(unsigned int base, enum avmcardtype cardtype) argument 386 t1outp(unsigned int base, unsigned short offset, unsigned char value) argument 393 t1inp(unsigned int base, unsigned short offset) argument 399 t1_isfastlink(unsigned int base) argument 404 t1_fifostatus(unsigned int base) argument 409 t1_get_slice(unsigned int base, unsigned char *dp) argument 462 t1_put_slice(unsigned int base, unsigned char *dp, unsigned int len) argument 495 t1_disable_irq(unsigned int base) argument 500 t1_reset(unsigned int base) argument 512 b1_setinterrupt(unsigned int base, unsigned irq, enum avmcardtype cardtype) argument [all...] |
/drivers/usb/dwc3/ |
H A D | io.h | 27 static inline u32 dwc3_readl(void __iomem *base, u32 offset) argument 37 value = readl(base + offs); 45 base - DWC3_GLOBALS_REGS_START + offset, value); 50 static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) argument 59 writel(value, base + offs); 67 base - DWC3_GLOBALS_REGS_START + offset, value);
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/drivers/irqchip/ |
H A D | irq-sirfsoc.c | 31 sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) argument 43 gc->reg_base = base; 52 void __iomem *base = sirfsoc_irqdomain->host_data; local 55 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); 62 void __iomem *base = of_iomap(np, 0); local 63 if (!base) 67 &irq_generic_chip_ops, base); 69 sirfsoc_alloc_gc(base, 0, 32); 70 sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32); 72 writel_relaxed(0, base 95 void __iomem *base = sirfsoc_irqdomain->host_data; local 107 void __iomem *base = sirfsoc_irqdomain->host_data; local [all...] |
/drivers/video/fbdev/omap2/dss/ |
H A D | hdmi5_core.c | 54 void __iomem *base = core->base; local 69 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); 70 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, 75 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); 79 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, 81 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, 86 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, 88 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, 93 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADD 133 void __iomem *base = core->base; local 143 void __iomem *base = core->base; local 322 void __iomem *base = core->base; local 386 void __iomem *base = core->base; local 424 void __iomem *base = core->base; local 480 void __iomem *base = core->base; local 522 void __iomem *base = core->base; local 538 void __iomem *base = core->base; local 587 void __iomem *base = core->base; local 653 void __iomem *base = core->base; local 789 void __iomem *base = core->base; local [all...] |
/drivers/gpu/drm/msm/adreno/ |
H A D | a3xx_gpu.h | 30 struct adreno_gpu base; member in struct:a3xx_gpu 37 #define to_a3xx_gpu(x) container_of(x, struct a3xx_gpu, base)
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/drivers/gpu/drm/nouveau/ |
H A D | nv10_fence.h | 8 struct nouveau_fence_chan base; member in struct:nv10_fence_chan 14 struct nouveau_fence_priv base; member in struct:nv10_fence_priv
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