Searched refs:basereg (Results 1 - 4 of 4) sorted by relevance

/drivers/ide/
H A Dcs5530.c55 unsigned long basereg = CS5530_BASEREG(hwif); local
56 unsigned int format = (inl(basereg + 4) >> 31) & 1;
59 outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
105 unsigned long basereg; local
116 basereg = CS5530_BASEREG(hwif);
117 reg = inl(basereg + 4); /* get drive0 config register */
120 outl(timings, basereg + 4); /* write drive0 config register */
126 outl(reg, basereg + 4); /* write drive0 config register */
127 outl(timings, basereg + 12); /* write drive1 config register */
231 unsigned long basereg; local
[all...]
H A Dsc1200.c85 unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0; local
87 pci_read_config_dword(pdev, basereg + 4, &format);
91 pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
131 unsigned int basereg = hwif->channel ? 0x50 : 0x40; local
159 pci_read_config_dword(dev, basereg + 4, &reg);
161 pci_write_config_dword(dev, basereg + 4, timings);
163 pci_write_config_dword(dev, basereg + 12, timings);
/drivers/bus/
H A Dmvebu-mbus.c140 u32 basereg = readl(addr + WIN_BASE_OFF); local
149 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
150 *base |= (basereg & WIN_BASE_LOW);
330 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); local
340 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
341 base |= basereg & DDR_BASE_CS_LOW_MASK;
/drivers/gpu/drm/
H A Ddrm_dp_mst_topology.c1977 int basereg = up ? DP_SIDEBAND_MSG_UP_REQ_BASE : DP_SIDEBAND_MSG_DOWN_REP_BASE; local
1981 ret = drm_dp_dpcd_read(mgr->aux, basereg,
1999 ret = drm_dp_dpcd_read(mgr->aux, basereg + curreply,

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