/drivers/clk/berlin/ |
H A D | common.h | 25 u8 bit_idx; member in struct:berlin2_gate_data
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H A D | bg2q.c | 356 gd->bit_idx, 0, &lock);
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H A D | bg2.c | 661 gd->bit_idx, 0, &lock);
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/drivers/clk/ |
H A D | clk-gate.c | 57 reg = BIT(gate->bit_idx + 16); 59 reg |= BIT(gate->bit_idx); 64 reg |= BIT(gate->bit_idx); 66 reg &= ~BIT(gate->bit_idx); 96 reg ^= BIT(gate->bit_idx); 98 reg &= BIT(gate->bit_idx); 117 * @bit_idx: which bit in the register controls gating of this clock 123 void __iomem *reg, u8 bit_idx, 131 if (bit_idx > 16) { 152 gate->bit_idx 121 clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) argument [all...] |
/drivers/clk/hisilicon/ |
H A D | clkgate-separated.c | 43 u8 bit_idx; /* bits in enable/disable register */ member in struct:clkgate_separated 57 reg = BIT(sclk->bit_idx); 74 reg = BIT(sclk->bit_idx); 88 reg &= BIT(sclk->bit_idx); 102 void __iomem *reg, u8 bit_idx, 122 sclk->bit_idx = bit_idx; 99 hisi_register_clkgate_sep(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) argument
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H A D | clk.h | 88 u8 bit_idx; member in struct:hisi_gate_clock
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H A D | clk.c | 192 clks[i].bit_idx, 220 clks[i].bit_idx,
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/drivers/xen/events/ |
H A D | events_2l.c | 167 int word_idx, bit_idx; local 177 bit_idx = evtchn % BITS_PER_LONG; 178 if (active_evtchns(cpu, s, word_idx) & (1ULL << bit_idx)) 204 bit_idx = 0; 210 bit_idx = 0; /* usually scan entire word from start */ 225 bit_idx = start_bit_idx; 232 bits = MASK_LSBS(pending_bits, bit_idx); 238 bit_idx = EVTCHN_FIRST_BIT(bits); 241 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx; 247 bit_idx [all...] |
/drivers/clk/mvebu/ |
H A D | common.h | 42 int bit_idx; member in struct:clk_gating_soc_desc
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H A D | common.c | 196 if (clkspec->args[0] == gate->bit_idx) 242 desc[n].flags, base, desc[n].bit_idx,
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/drivers/clk/sunxi/ |
H A D | clk-a10-hosc.c | 49 gate->bit_idx = SUNXI_OSC24M_GATE;
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H A D | clk-a20-gmac.c | 89 gate->bit_idx = SUN7I_A20_GMAC_GPIT;
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H A D | clk-factors.c | 210 gate->bit_idx = data->enable;
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/drivers/clk/pxa/ |
H A D | clk-pxa.h | 90 .gate = { .reg = (void __iomem *)_cken_reg, .bit_idx = _cken_bit }, \
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/drivers/clk/socfpga/ |
H A D | clk-pll.c | 122 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
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H A D | clk-gate.c | 209 socfpga_clk->hw.bit_idx = clk_gate[1];
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/drivers/clk/samsung/ |
H A D | clk-exynos-clkout.c | 94 clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
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H A D | clk.h | 226 * @bit_idx: bit index of the gate control bit-field in @reg. 237 u8 bit_idx; member in struct:samsung_gate_clock 250 .bit_idx = b, \
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H A D | clk.c | 260 list->bit_idx, list->gate_flags, &ctx->lock);
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/drivers/clk/rockchip/ |
H A D | clk.c | 77 gate->bit_idx = gate_shift; 123 gate->bit_idx = gate_shift;
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/drivers/clk/st/ |
H A D | clk-flexgen.c | 201 fgxbar->pgate.bit_idx = xbar_shift + 6; 211 fgxbar->fgate.bit_idx = 6;
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H A D | clkgen-mux.c | 770 gate->bit_idx = i;
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H A D | clkgen-pll.c | 566 gate->bit_idx = pll_data->odf_gate[odf].shift;
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/drivers/net/wireless/ath/wcn36xx/ |
H A D | smd.c | 1691 int arr_idx, bit_idx; local 1699 bit_idx = cap % 32; 1700 bitmap[arr_idx] |= (1 << bit_idx); 1705 int arr_idx, bit_idx; local 1714 bit_idx = cap % 32; 1715 ret = (bitmap[arr_idx] & (1 << bit_idx)) ? 1 : 0; 1721 int arr_idx, bit_idx; local 1729 bit_idx = cap % 32; 1730 bitmap[arr_idx] &= ~(1 << bit_idx);
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/drivers/net/ethernet/intel/i40e/ |
H A D | i40e_virtchnl_pf.c | 790 u32 reg_idx, bit_idx; local 824 bit_idx = (hw->func_caps.vf_base_id + vf_id) % 32; 825 wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), (1 << bit_idx)); 1865 u32 reg, reg_idx, bit_idx, vf_id; local 1875 bit_idx = (hw->func_caps.vf_base_id + vf_id) % 32; 1879 if (reg & (1 << bit_idx)) { 1881 wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), (1 << bit_idx));
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