Searched refs:bit_idx (Results 1 - 25 of 26) sorted by relevance

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/drivers/clk/berlin/
H A Dcommon.h25 u8 bit_idx; member in struct:berlin2_gate_data
H A Dbg2q.c356 gd->bit_idx, 0, &lock);
H A Dbg2.c661 gd->bit_idx, 0, &lock);
/drivers/clk/
H A Dclk-gate.c57 reg = BIT(gate->bit_idx + 16);
59 reg |= BIT(gate->bit_idx);
64 reg |= BIT(gate->bit_idx);
66 reg &= ~BIT(gate->bit_idx);
96 reg ^= BIT(gate->bit_idx);
98 reg &= BIT(gate->bit_idx);
117 * @bit_idx: which bit in the register controls gating of this clock
123 void __iomem *reg, u8 bit_idx,
131 if (bit_idx > 16) {
152 gate->bit_idx
121 clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) argument
[all...]
/drivers/clk/hisilicon/
H A Dclkgate-separated.c43 u8 bit_idx; /* bits in enable/disable register */ member in struct:clkgate_separated
57 reg = BIT(sclk->bit_idx);
74 reg = BIT(sclk->bit_idx);
88 reg &= BIT(sclk->bit_idx);
102 void __iomem *reg, u8 bit_idx,
122 sclk->bit_idx = bit_idx;
99 hisi_register_clkgate_sep(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) argument
H A Dclk.h88 u8 bit_idx; member in struct:hisi_gate_clock
H A Dclk.c192 clks[i].bit_idx,
220 clks[i].bit_idx,
/drivers/xen/events/
H A Devents_2l.c167 int word_idx, bit_idx; local
177 bit_idx = evtchn % BITS_PER_LONG;
178 if (active_evtchns(cpu, s, word_idx) & (1ULL << bit_idx))
204 bit_idx = 0;
210 bit_idx = 0; /* usually scan entire word from start */
225 bit_idx = start_bit_idx;
232 bits = MASK_LSBS(pending_bits, bit_idx);
238 bit_idx = EVTCHN_FIRST_BIT(bits);
241 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx;
247 bit_idx
[all...]
/drivers/clk/mvebu/
H A Dcommon.h42 int bit_idx; member in struct:clk_gating_soc_desc
H A Dcommon.c196 if (clkspec->args[0] == gate->bit_idx)
242 desc[n].flags, base, desc[n].bit_idx,
/drivers/clk/sunxi/
H A Dclk-a10-hosc.c49 gate->bit_idx = SUNXI_OSC24M_GATE;
H A Dclk-a20-gmac.c89 gate->bit_idx = SUN7I_A20_GMAC_GPIT;
H A Dclk-factors.c210 gate->bit_idx = data->enable;
/drivers/clk/pxa/
H A Dclk-pxa.h90 .gate = { .reg = (void __iomem *)_cken_reg, .bit_idx = _cken_bit }, \
/drivers/clk/socfpga/
H A Dclk-pll.c122 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
H A Dclk-gate.c209 socfpga_clk->hw.bit_idx = clk_gate[1];
/drivers/clk/samsung/
H A Dclk-exynos-clkout.c94 clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
H A Dclk.h226 * @bit_idx: bit index of the gate control bit-field in @reg.
237 u8 bit_idx; member in struct:samsung_gate_clock
250 .bit_idx = b, \
H A Dclk.c260 list->bit_idx, list->gate_flags, &ctx->lock);
/drivers/clk/rockchip/
H A Dclk.c77 gate->bit_idx = gate_shift;
123 gate->bit_idx = gate_shift;
/drivers/clk/st/
H A Dclk-flexgen.c201 fgxbar->pgate.bit_idx = xbar_shift + 6;
211 fgxbar->fgate.bit_idx = 6;
H A Dclkgen-mux.c770 gate->bit_idx = i;
H A Dclkgen-pll.c566 gate->bit_idx = pll_data->odf_gate[odf].shift;
/drivers/net/wireless/ath/wcn36xx/
H A Dsmd.c1691 int arr_idx, bit_idx; local
1699 bit_idx = cap % 32;
1700 bitmap[arr_idx] |= (1 << bit_idx);
1705 int arr_idx, bit_idx; local
1714 bit_idx = cap % 32;
1715 ret = (bitmap[arr_idx] & (1 << bit_idx)) ? 1 : 0;
1721 int arr_idx, bit_idx; local
1729 bit_idx = cap % 32;
1730 bitmap[arr_idx] &= ~(1 << bit_idx);
/drivers/net/ethernet/intel/i40e/
H A Di40e_virtchnl_pf.c790 u32 reg_idx, bit_idx; local
824 bit_idx = (hw->func_caps.vf_base_id + vf_id) % 32;
825 wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), (1 << bit_idx));
1865 u32 reg, reg_idx, bit_idx, vf_id; local
1875 bit_idx = (hw->func_caps.vf_base_id + vf_id) % 32;
1879 if (reg & (1 << bit_idx)) {
1881 wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), (1 << bit_idx));

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