Searched refs:cfg (Results 1 - 25 of 651) sorted by relevance

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/drivers/media/platform/exynos-gsc/
H A Dgsc-regs.c26 u32 cfg; local
29 cfg = readl(dev->regs + GSC_SW_RESET);
30 if (!cfg)
40 u32 cfg; local
42 cfg = readl(dev->regs + GSC_IRQ);
44 cfg |= GSC_IRQ_FRMDONE_MASK;
46 cfg &= ~GSC_IRQ_FRMDONE_MASK;
47 writel(cfg, dev->regs + GSC_IRQ);
52 u32 cfg; local
54 cfg
65 u32 cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK); local
79 u32 cfg = readl(dev->regs + GSC_OUT_BASE_ADDR_Y_MASK); local
115 u32 cfg = readl(dev->regs + GSC_IN_CON); local
128 u32 cfg; local
150 u32 cfg; local
171 u32 cfg; local
226 u32 cfg = readl(dev->regs + GSC_OUT_CON); local
241 u32 cfg; local
270 u32 cfg; local
291 u32 cfg; local
350 u32 cfg; local
362 u32 cfg; local
374 u32 cfg; local
408 u32 cfg; local
425 u32 cfg; local
[all...]
/drivers/media/platform/exynos4-is/
H A Dfimc-lite-reg.c26 u32 cfg; local
28 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
29 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ;
30 writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
33 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
34 if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY)
39 cfg |= FLITE_REG_CIGCTRL_SWRST;
40 writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
45 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); local
46 cfg
59 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2); local
66 u32 cfg, intsrc; local
88 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); local
95 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); local
106 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); local
134 u32 cfg; local
164 u32 cfg; local
182 u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL); local
194 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); local
222 u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT); local
240 u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT); local
252 u32 cfg; local
270 u32 cfg; local
289 u32 cfg; local
303 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); local
345 u32 cfg = readl(dev->regs + registers[i].offset); local
[all...]
H A Dfimc-reg.c24 u32 cfg; local
26 cfg = readl(dev->regs + FIMC_REG_CISRCFMT);
27 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
28 writel(cfg, dev->regs + FIMC_REG_CISRCFMT);
31 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
32 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL);
33 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
36 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
37 cfg &= ~FIMC_REG_CIGCTRL_SWRST;
38 writel(cfg, de
76 u32 cfg, flip; local
109 u32 cfg; local
154 u32 cfg; local
175 u32 cfg; local
216 u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE); local
226 u32 cfg = readl(dev->regs + FIMC_REG_CIOCTRL); local
238 u32 cfg, shfactor; local
257 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); local
319 u32 cfg; local
352 u32 cfg; local
368 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT); local
378 u32 cfg = 0; local
395 u32 cfg; local
428 u32 cfg; local
510 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL); local
525 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); local
534 u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE); local
562 u32 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL); local
606 u32 bus_width, cfg = 0; local
653 u32 cfg = readl(fimc->regs + FIMC_REG_CIWDOFST); local
673 u32 cfg, tmp; local
736 u32 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); local
743 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); local
753 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL); local
[all...]
/drivers/media/platform/s3c-camif/
H A Dcamif-regs.c21 u32 cfg; local
23 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT);
24 cfg |= CISRCFMT_ITU601_8BIT;
25 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg);
28 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL);
29 cfg |= CIGCTRL_SWRST;
31 cfg |= CIGCTRL_IRQ_LEVEL;
32 camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg);
35 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL);
36 cfg
43 u32 cfg = camif_read(vp->camif, S3C_CAMIF_REG_CIGCTRL); local
54 u32 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); local
73 unsigned int i, cfg; local
110 u32 cfg; local
136 u32 cfg; local
157 u32 cfg; local
174 u32 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); local
224 u32 cfg; local
264 u32 cfg; local
294 u32 cfg = camif_read(vp->camif, S3C_CAMIF_REG_MSCTRL(vp->id)); local
303 u32 cfg; local
351 u32 cfg = camif_read(vp->camif, local
368 u32 cfg, shfactor, addr; local
387 u32 cfg; local
434 u32 cfg; local
491 u32 cfg; local
504 u32 cfg; local
517 u32 cfg; local
540 u32 cfg; local
603 u32 cfg = readl(camif->io_base + registers[i].offset); local
[all...]
/drivers/pci/
H A Dhtirq.c38 struct ht_irq_cfg *cfg = irq_get_handler_data(irq); local
41 if (cfg->msg.address_lo != msg->address_lo) {
42 pci_write_config_byte(cfg->dev, cfg->pos + 2, cfg->idx);
43 pci_write_config_dword(cfg->dev, cfg->pos + 4, msg->address_lo);
45 if (cfg->msg.address_hi != msg->address_hi) {
46 pci_write_config_byte(cfg->dev, cfg
57 struct ht_irq_cfg *cfg = irq_get_handler_data(irq); local
63 struct ht_irq_cfg *cfg = irq_data_get_irq_handler_data(data); local
72 struct ht_irq_cfg *cfg = irq_data_get_irq_handler_data(data); local
89 struct ht_irq_cfg *cfg; local
161 struct ht_irq_cfg *cfg; local
[all...]
/drivers/net/wireless/brcm80211/brcmfmac/
H A Dbtcoex.h24 int brcmf_btcoex_attach(struct brcmf_cfg80211_info *cfg);
25 void brcmf_btcoex_detach(struct brcmf_cfg80211_info *cfg);
/drivers/cpufreq/
H A Ds3c24xx-cpufreq-debugfs.c39 struct s3c_cpufreq_config *cfg; local
42 cfg = s3c_cpufreq_getconfig();
43 if (!cfg) {
48 brd = cfg->board;
79 struct s3c_cpufreq_config *cfg; local
81 cfg = s3c_cpufreq_getconfig();
82 if (!cfg) {
87 seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk);
89 cfg->freq.hclk, print_ns(cfg
122 struct s3c_cpufreq_config *cfg; local
[all...]
H A Ds3c2410-cpufreq.c33 static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) argument
37 if (cfg->divs.h_divisor == 2)
40 if (cfg->divs.p_divisor != cfg->divs.h_divisor)
46 static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) argument
52 fclk = cfg->freq.fclk;
53 hclk_max = cfg->max.hclk;
55 cfg->freq.armclk = fclk;
60 hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
63 if (hclk > cfg
[all...]
H A Ds3c2412-cpufreq.c41 static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) argument
47 fclk = cfg->freq.fclk;
48 armclk = cfg->freq.armclk;
49 hclk_max = cfg->max.hclk;
60 __func__, cfg->freq.fclk, cfg->freq.armclk,
61 cfg->freq.hclk, cfg->freq.pclk);
70 cfg->divs.arm_divisor = armdiv;
77 cfg
116 s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) argument
143 s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) argument
[all...]
/drivers/media/tuners/
H A Dfc0012-priv.h26 const struct fc0012_config *cfg; member in struct:fc0012_priv
H A Dtua9001_priv.h30 struct tua9001_config *cfg; member in struct:tua9001_priv
H A Dfc2580.h42 struct i2c_adapter *i2c, const struct fc2580_config *cfg);
45 struct i2c_adapter *i2c, const struct fc2580_config *cfg)
44 fc2580_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct fc2580_config *cfg) argument
H A Dmt2266.h28 extern struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg);
30 static inline struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg) argument
H A Dqt1010.h36 * @param cfg tuner hw based configuration
42 struct qt1010_config *cfg);
46 struct qt1010_config *cfg)
44 qt1010_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct qt1010_config *cfg) argument
H A Dqm1d1c0042.c53 struct qm1d1c0042_config cfg; member in struct:qm1d1c0042_state
60 return container_of(c, struct qm1d1c0042_state, cfg);
122 __func__, state->cfg.fe->dvb->num, state->cfg.fe->id);
131 struct qm1d1c0042_config *cfg; local
134 cfg = priv_cfg;
136 if (cfg->fe)
137 state->cfg.fe = cfg->fe;
139 if (cfg
399 struct qm1d1c0042_config *cfg; local
[all...]
H A Dm88ts2022_priv.h24 struct m88ts2022_config cfg; member in struct:m88ts2022_dev
H A Dmt2131_priv.h37 struct mt2131_config *cfg; member in struct:mt2131_priv
/drivers/regulator/
H A Dfixed-helper.c8 struct fixed_voltage_config cfg; member in struct:fixed_regulator_data
17 kfree(data->cfg.supply_name);
38 data->cfg.supply_name = kstrdup(name, GFP_KERNEL);
39 if (!data->cfg.supply_name) {
44 data->cfg.microvolts = uv;
45 data->cfg.gpio = -EINVAL;
46 data->cfg.enabled_at_boot = 1;
47 data->cfg.init_data = &data->init_data;
55 data->pdev.dev.platform_data = &data->cfg;
/drivers/gpu/drm/exynos/
H A Dexynos_drm_gsc.c84 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
400 u32 cfg; local
404 cfg = (GSC_SW_RESET_SRESET);
405 gsc_write(cfg, GSC_SW_RESET);
409 cfg = gsc_read(GSC_SW_RESET);
410 if (!cfg)
415 if (cfg) {
421 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
422 cfg |
457 u32 cfg; local
488 u32 cfg; local
564 u32 cfg; local
612 u32 cfg; local
670 u32 cfg; local
758 u32 cfg; local
831 u32 cfg; local
911 u32 cfg; local
1014 u32 cfg; local
1034 u32 cfg; local
1086 u32 cfg, i, buf_num = GSC_REG_SZ; local
1105 u32 cfg; local
1222 u32 cfg, curr_index, i; local
1257 u32 cfg, curr_index, i; local
1521 u32 cfg; local
1616 u32 cfg; local
[all...]
H A Dexynos_drm_fimc.c198 u32 cfg; local
201 cfg = fimc_read(ctx, EXYNOS_CISTATUS);
202 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg))
230 u32 cfg; local
234 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
235 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
244 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A |
248 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B |
253 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
260 fimc_write(ctx, cfg, EXYNOS_CIGCTR
266 u32 cfg; local
291 u32 cfg; local
306 u32 cfg; local
350 u32 cfg; local
367 u32 cfg; local
393 u32 cfg; local
410 u32 cfg; local
483 u32 cfg; local
600 u32 cfg, h1, h2, v1, v2; local
637 u32 cfg; local
755 u32 cfg; local
834 u32 cfg; local
902 u32 cfg; local
956 u32 cfg, cfg_ext, shfactor; local
1022 u32 cfg, cfg_ext; local
1065 u32 cfg; local
1127 u32 cfg; local
1566 u32 cfg; local
[all...]
/drivers/block/rsxx/
H A Dconfig.c32 static void initialize_config(struct rsxx_card_cfg *cfg) argument
34 cfg->hdr.version = RSXX_CFG_VERSION;
36 cfg->data.block_size = RSXX_HW_BLK_SIZE;
37 cfg->data.stripe_size = RSXX_HW_BLK_SIZE;
38 cfg->data.vendor_id = RSXX_VENDOR_ID_IBM;
39 cfg->data.cache_order = (-1);
40 cfg->data.intr_coal.mode = RSXX_INTR_COAL_DISABLED;
41 cfg->data.intr_coal.count = 0;
42 cfg->data.intr_coal.latency = 0;
45 static u32 config_data_crc32(struct rsxx_card_cfg *cfg) argument
69 config_data_swab(struct rsxx_card_cfg *cfg) argument
78 config_data_le_to_cpu(struct rsxx_card_cfg *cfg) argument
87 config_data_cpu_to_le(struct rsxx_card_cfg *cfg) argument
100 struct rsxx_card_cfg cfg; local
[all...]
/drivers/media/dvb-frontends/
H A Da8293.h32 struct i2c_adapter *i2c, const struct a8293_config *cfg);
35 struct i2c_adapter *i2c, const struct a8293_config *cfg)
34 a8293_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct a8293_config *cfg) argument
H A Ditd1000.h33 extern struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg);
35 static inline struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg) argument
/drivers/media/platform/davinci/
H A Dvpbe.c65 struct vpbe_config *cfg = vpbe_dev->cfg; local
68 return ((index == 0) ? &cfg->venc :
69 &cfg->ext_encoders[index-1]);
75 * @vpbe_config - ptr to vpbe cfg
80 static int vpbe_find_encoder_sd_index(struct vpbe_config *cfg, argument
83 char *encoder_name = cfg->outputs[index].subdev_name;
87 if (!strcmp(encoder_name, cfg->venc.module_name))
90 for (i = 0; i < cfg->num_ext_encoders; i++) {
92 cfg
132 struct vpbe_config *cfg = vpbe_dev->cfg; local
147 struct vpbe_config *cfg = vpbe_dev->cfg; local
181 struct vpbe_config *cfg = vpbe_dev->cfg; local
201 struct vpbe_config *cfg = vpbe_dev->cfg; local
228 struct vpbe_config *cfg = vpbe_dev->cfg; local
299 struct vpbe_config *cfg = vpbe_dev->cfg; local
335 struct vpbe_config *cfg = vpbe_dev->cfg; local
405 struct vpbe_config *cfg = vpbe_dev->cfg; local
436 struct vpbe_config *cfg = vpbe_dev->cfg; local
496 struct vpbe_config *cfg = vpbe_dev->cfg; local
813 struct vpbe_config *cfg; local
[all...]
/drivers/usb/serial/
H A Dkl5kusb105.c115 struct klsi_105_port_settings cfg; member in struct:klsi_105_private
225 priv->cfg.pktlen = 5;
226 priv->cfg.baudrate = kl5kusb105a_sio_b9600;
227 priv->cfg.databits = kl5kusb105a_dtb_8;
228 priv->cfg.unknown1 = 0;
229 priv->cfg.unknown2 = 1;
259 struct klsi_105_port_settings *cfg; local
269 cfg = kmalloc(sizeof(*cfg), GFP_KERNEL);
270 if (!cfg)
407 struct klsi_105_port_settings *cfg; local
[all...]

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