| /drivers/video/fbdev/ |
| H A D | sstfb.c | 969 u8 cr0, cc; local
977 cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */
984 sst_dac_write(DACREG_RMR, (cr0 & 0xf0)
1015 cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED);
1060 u8 cr0; local
1068 cr0 = sst_dac_read(DACREG_RMR);
1075 /* cr0 */
1078 sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP);
|
| /drivers/s390/char/ |
| H A D | sclp.c | 560 unsigned long cr0, cr0_sync; local
581 __ctl_store(cr0, 0, 0);
582 cr0_sync = cr0;
597 __ctl_load(cr0, 0, 0);
|
| /drivers/spi/ |
| H A D | spi-dw.c | 38 u16 cr0; member in struct:chip_data
371 u32 cr0 = 0; local
413 cr0 = chip->cr0;
433 cr0 = (bits - 1)
452 cr0 &= ~SPI_TMOD_MASK;
453 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
480 if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
483 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
484 dw_writew(dws, DW_SPI_CTRL0, cr0);
[all...] |
| H A D | spi-ep93xx.c | 317 u16 cr0; local
324 cr0 = div_scr << SSPCR0_SCR_SHIFT;
325 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT;
326 cr0 |= dss;
330 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x\n", cr0);
333 ep93xx_spi_write_u16(espi, SSPCR0, cr0);
|
| H A D | spi-pl022.c | 412 * @cr0: Value of control register CR0 of SSP - on later ST variants this
428 u32 cr0; member in struct:chip_data
573 writel(chip->cr0, SSP_CR0(pl022->virtbase));
575 writew(chip->cr0, SSP_CR0(pl022->virtbase));
1951 chip->cr0 = 0;
1984 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1986 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1988 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1993 SSP_WRITE_BITS(chip->cr0, bits - 1,
2010 SSP_WRITE_BITS(chip->cr0, bit
[all...] |
| H A D | spi-pxa2xx.c | 612 u32 cr0; local
690 cr0 = chip->cr0;
734 cr0 = clk_div
775 if ((read_SSCR0(reg) != cr0)
780 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
786 write_SSCR0(cr0, reg);
962 chip->cr0 = clk_div
979 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
984 / (1 + ((chip->cr0
[all...] |
| H A D | spi-pxa2xx.h | 94 u32 cr0; member in struct:chip_data
|
| H A D | spi-rockchip.c | 495 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) local
498 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
499 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
500 cr0 |= (rs->tmode << CR0_XFM_OFFSET);
501 cr0 |= (rs->type << CR0_FRF_OFFSET);
523 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
535 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
|
| H A D | spi-txx9.c | 211 u32 cr0; local
218 cr0 = txx9spi_rd(c, TXx9_SPCR0);
219 cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
220 cr0 |= (count - 1) << 12;
222 cr0 |= TXx9_SPCR0_RBSIE;
223 txx9spi_wr(c, cr0, TXx9_SPCR0);
|
| /drivers/input/touchscreen/ |
| H A D | mc13783_ts.c | 75 int cr0, cr1; local
87 cr0 = (priv->sample[2] >> 12) & 0xfff;
92 x0, x1, x2, y0, y1, y2, cr0, cr1);
97 cr0 = (cr0 + cr1) / 2;
99 if (!cr0 || !sample_tolerance ||
103 if (cr0) {
108 x1, y1, 0x1000 - cr0);
114 cr0 ? 0x1000 - cr0
[all...] |
| /drivers/cpufreq/ |
| H A D | powernow-k6.c | 105 unsigned long cr0; local
114 cr0 = read_cr0();
115 write_cr0(cr0 | X86_CR0_CD);
129 write_cr0(cr0);
|
| /drivers/crypto/ccp/ |
| H A D | ccp-ops.c | 198 u32 cr0, cmd; local
208 cr0 = (cmd_q->id << REQ0_CMD_Q_SHIFT)
213 cr0 |= REQ0_STOP_ON_COMPLETE
217 cr0 |= REQ0_INT_ON_COMPLETE;
230 iowrite32(cr0, ccp->io_regs + CMD_REQ0);
234 if (cr0 & REQ0_INT_ON_COMPLETE) {
|