/drivers/crypto/qat/qat_common/ |
H A D | icp_qat_hal.h | 102 #define SET_CAP_CSR(handle, csr, val) \ 103 ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val) 104 #define GET_CAP_CSR(handle, csr) \ 105 ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr) 106 #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val) 107 #define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr) 111 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr)) [all...] |
H A D | adf_transport_debug.c | 90 void __iomem *csr = ring->bank->csr_addr; local 96 head = READ_CSR_RING_HEAD(csr, bank->bank_number, 98 tail = READ_CSR_RING_TAIL(csr, bank->bank_number, 100 empty = READ_CSR_E_STAT(csr, bank->bank_number); 224 void __iomem *csr = bank->csr_addr; local 230 head = READ_CSR_RING_HEAD(csr, bank->bank_number, 232 tail = READ_CSR_RING_TAIL(csr, bank->bank_number, 234 empty = READ_CSR_E_STAT(csr, bank->bank_number);
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/drivers/crypto/qat/qat_dh895xcc/ |
H A D | adf_hw_arbiter.c | 92 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; local 100 WRITE_CSR_ARB_SARCONFIG(csr, arb, arb_cfg); 105 WRITE_CSR_ARB_WEIGHT(csr, arb, i, 0xFFFFFFFF); 109 WRITE_CSR_ARB_RESPORDERING(csr, i, 0xFFFFFFFF); 113 WRITE_CSR_ARB_WQCFG(csr, i, i); 122 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, *(thd_2_arb_cfg + i)); 136 void __iomem *csr; local 142 csr = accel_dev->transport->banks[0].csr_addr; 146 WRITE_CSR_ARB_SARCONFIG(csr, i, 0); 150 WRITE_CSR_ARB_WQCFG(csr, [all...] |
H A D | adf_dh895xcc_hw_data.c | 161 void __iomem *csr = misc_bar->virt_addr; local 166 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i)); 168 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); 169 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i)); 171 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val); 176 val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i)); 178 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); 179 val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i)); 181 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val);
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H A D | adf_admin.c | 106 void __iomem *csr = pmisc->virt_addr; local 107 void __iomem *mailbox = csr + ADF_DH895XCC_MAILBOX_BASE_OFFSET; 122 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGUR_OFFSET, reg_val >> 32); 123 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGLR_OFFSET, reg_val);
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/drivers/staging/gdm72xx/ |
H A D | gdm_qos.c | 100 qcb->csr[i].qos_buf_count = 0; 101 qcb->csr[i].enabled = false; 127 qcb->csr[i].qos_buf_count = 0; 128 qcb->csr[i].enabled = false; 143 static int chk_ipv4_rule(struct gdm_wimax_csr_s *csr, u8 *stream, u8 *port) argument 147 if (csr->classifier_rule_en&IPTYPEOFSERVICE) { 148 if (((stream[1] & csr->ip2s_mask) < csr->ip2s_lo) || 149 ((stream[1] & csr->ip2s_mask) > csr [all...] |
/drivers/watchdog/ |
H A D | shwdt.c | 89 u8 csr; local 99 csr = sh_wdt_read_csr(); 100 csr |= WTCSR_WT | clock_division_ratio; 101 sh_wdt_write_csr(csr); 113 csr = sh_wdt_read_csr(); 114 csr |= WTCSR_TME; 115 csr &= ~WTCSR_RSTS; 116 sh_wdt_write_csr(csr); 119 csr = sh_wdt_read_rstcsr(); 120 csr 132 u8 csr; local 185 u8 csr; local [all...] |
/drivers/usb/musb/ |
H A D | musb_gadget_ep0.c | 264 u16 csr; variable 287 csr = musb_readw(regs, MUSB_TXCSR); 288 csr |= MUSB_TXCSR_CLRDATATOG | 290 csr &= ~(MUSB_TXCSR_P_SENDSTALL | 293 musb_writew(regs, MUSB_TXCSR, csr); 295 csr = musb_readw(regs, MUSB_RXCSR); 296 csr |= MUSB_RXCSR_CLRDATATOG | 298 csr &= ~(MUSB_RXCSR_P_SENDSTALL | 300 musb_writew(regs, MUSB_RXCSR, csr); 428 u16 csr; variable 490 u16 count, csr; local 547 u16 csr = MUSB_CSR0_TXPKTRDY; local 668 u16 csr; local 1022 u16 csr; local [all...] |
H A D | musb_gadget.c | 262 u16 fifo_count = 0, csr; local 281 csr = musb_readw(epio, MUSB_TXCSR); 287 if (csr & MUSB_TXCSR_TXPKTRDY) { 289 musb_ep->end_point.name, csr); 293 if (csr & MUSB_TXCSR_P_SENDSTALL) { 295 musb_ep->end_point.name, csr); 301 csr); 335 csr &= ~(MUSB_TXCSR_AUTOSET 337 musb_writew(epio, MUSB_TXCSR, csr 339 csr 444 u16 csr; local 568 u16 csr = musb_readw(epio, MUSB_RXCSR); local 832 u16 csr; local 962 u16 csr; local 1360 u16 csr; local 1480 u16 csr; local [all...] |
H A D | musbhsdma.c | 118 u16 csr = 0; local 124 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; 127 csr |= MUSB_HSDMA_BURSTMODE_INCR16 130 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) 144 csr); 201 u16 csr; local 212 csr = musb_readw(mbase, offset); 213 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 214 musb_writew(mbase, offset, csr); 215 csr 256 u16 csr; local [all...] |
H A D | musb_cppi41.c | 61 u16 csr; local 69 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR); 70 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; 79 u16 csr; local 88 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 89 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; 97 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE; 98 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr); 111 u16 csr; local 114 csr 127 u16 csr; local 529 u16 csr; local [all...] |
H A D | musb_host.c | 114 u16 csr; local 118 csr = musb_readw(epio, MUSB_TXCSR); 119 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { 120 if (csr != lastcsr) 121 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); 122 lastcsr = csr; 123 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY; 124 musb_writew(epio, MUSB_TXCSR, csr); 125 csr 137 u16 csr; local 327 u16 csr; local 434 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) argument 461 u16 csr; local 560 u16 csr; local 627 u16 csr; local 709 u16 csr; local 748 u16 csr; local 875 u16 csr; local 1087 u16 csr, len; local 2270 u16 csr; local [all...] |
/drivers/scsi/ |
H A D | sun3_scsi.c | 270 oldcsr = dregs->csr; 271 dregs->csr = 0; 273 if (dregs->csr == 0x1400) 276 dregs->csr = oldcsr; 344 dregs->csr = 0; 346 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR; 435 unsigned short csr = dregs->csr; local 439 dregs->csr &= ~CSR_DMA_ENABLE; 442 if(csr 606 unsigned short csr; local [all...] |
H A D | sun3x_esp.c | 109 u32 csr; local 112 csr = dma_read32(DMA_CSR); 113 if (!(csr & DMA_FIFO_ISDRAIN)) 116 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR); 154 u32 csr; local 160 csr = dma_read32(DMA_CSR); 161 csr |= DMA_ENABLE; 163 csr |= DMA_ST_WRITE; 165 csr &= ~DMA_ST_WRITE; 166 dma_write32(csr, DMA_CS 174 u32 csr = dma_read32(DMA_CSR); local [all...] |
/drivers/net/wireless/rt2x00/ |
H A D | rt2x00mmio.h | 36 *value = readl(rt2x00dev->csr.base + offset); 43 memcpy_fromio(value, rt2x00dev->csr.base + offset, length); 50 writel(value, rt2x00dev->csr.base + offset); 58 __iowrite32_copy(rt2x00dev->csr.base + offset, value, length >> 2);
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H A D | rt2x00debug.h | 62 RT2X00DEBUGFS_REGISTER_ENTRY(csr, u32);
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/drivers/power/reset/ |
H A D | xgene-reboot.c | 37 void *csr; member in struct:xgene_reboot_context 50 writel(ctx->mask, ctx->csr); 69 ctx->csr = of_iomap(pdev->dev.of_node, 0); 70 if (!ctx->csr) {
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/drivers/net/wireless/ath/wil6210/ |
H A D | interrupt.c | 78 iowrite32(WIL6210_IRQ_DISABLE, wil->csr + 85 iowrite32(WIL6210_IRQ_DISABLE, wil->csr + 92 iowrite32(WIL6210_IRQ_DISABLE, wil->csr + 101 iowrite32(WIL6210_IRQ_DISABLE, wil->csr + 109 iowrite32(WIL6210_IMC_TX, wil->csr + 116 iowrite32(WIL6210_IMC_RX, wil->csr + 123 iowrite32(WIL6210_IMC_MISC, wil->csr + 134 iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr + 152 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + 154 iowrite32(WIL_ICR_ICC_VALUE, wil->csr [all...] |
H A D | fw.c | 27 #define R(a) ioread32(wil->csr + HOSTADDR(a)) 29 #define W(a, v) do { iowrite32(v, wil->csr + HOSTADDR(a)); wmb(); } while (0)
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H A D | pcie_bus.c | 151 void __iomem *csr; local 188 csr = pci_ioremap_bar(pdev, 0); 189 if (!csr) { 195 dev_info(&pdev->dev, "CSR at %pR -> 0x%p\n", &pdev->resource[0], csr); 197 wil = wil_if_alloc(dev, csr); 242 pci_iounmap(pdev, csr); 254 void __iomem *csr = wil->csr; local 264 pci_iounmap(pdev, csr);
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H A D | ethtool.c | 52 itr_en = ioread32(wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL)); 54 itr_val = ioread32(wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_TRSH));
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/drivers/staging/media/omap24xx/ |
H A D | omap24xxcam-dma.c | 43 u32 csr; local 47 csr = omap24xxcam_reg_in(base, CAMDMA_CSR(i)); 49 omap24xxcam_reg_out(base, CAMDMA_CSR(i), csr); 57 u32 csr; local 59 csr = omap24xxcam_reg_in(base, CAMDMA_CSR(dmach)); 61 omap24xxcam_reg_out(base, CAMDMA_CSR(dmach), csr); 65 return csr; 244 static void omap24xxcam_dma_abort(struct omap24xxcam_dma *dma, u32 csr) argument 276 (*callback) (dma, csr, arg); 290 static void omap24xxcam_dma_stop(struct omap24xxcam_dma *dma, u32 csr) argument 303 u32 csr; local 389 omap24xxcam_sgdma_callback(struct omap24xxcam_dma *dma, u32 csr, void *arg) argument 548 u32 csr = CAMDMA_CSR_TRANS_ERR; local [all...] |
/drivers/usb/gadget/udc/ |
H A D | at91_udc.c | 95 u32 csr; local 102 csr = __raw_readl(ep->creg); 115 seq_printf(s, "csr %08x rxbytes=%d %s %s %s" EIGHTBITS "\n", 116 csr, 117 (csr & 0x07ff0000) >> 16, 118 (csr & (1 << 15)) ? "enabled" : "disabled", 119 (csr & (1 << 11)) ? "DATA1" : "DATA0", 120 types[(csr & 0x700) >> 8], 123 (!(csr & 0x700)) 124 ? ((csr 310 u32 csr; local 384 u32 csr = __raw_readl(creg); local 735 u32 csr; local 1011 u32 csr = __raw_readl(creg); local 1049 handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr) argument 1279 u32 csr = __raw_readl(creg); local [all...] |
/drivers/pcmcia/ |
H A D | pxa2xx_sharpsl.c | 62 unsigned short cpr, csr; local 70 csr = read_scoop_reg(scoop, SCOOP_CSR); 71 if (csr & 0x0004) { 79 csr |= SCOOP_DEV[skt->nr].keep_vs; 84 SCOOP_DEV[skt->nr].keep_vs = (csr & 0x00C0); 95 state->detect = (csr & 0x0004) ? 0 : 1; 96 state->ready = (csr & 0x0002) ? 1 : 0; 97 state->bvd1 = (csr & 0x0010) ? 1 : 0; 98 state->bvd2 = (csr & 0x0020) ? 1 : 0; 99 state->wrprot = (csr [all...] |
/drivers/mtd/devices/ |
H A D | ms02-nv.c | 192 mp->resource.csr = csr_res; 259 release_resource(mp->resource.csr); 260 kfree(mp->resource.csr); 274 volatile u32 *csr; local 281 csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); 282 if (*csr & KN02_CSR_BNK32M) 287 csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); 288 if (*csr & KN03_MCR_BNK32M)
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