/drivers/thunderbolt/ |
H A D | ctl.c | 14 #include "ctl.h" 18 struct tb_ctl *ctl; member in struct:ctl_pkg 43 #define tb_ctl_WARN(ctl, format, arg...) \ 44 dev_WARN(&(ctl)->nhi->pdev->dev, format, ## arg) 46 #define tb_ctl_err(ctl, format, arg...) \ 47 dev_err(&(ctl)->nhi->pdev->dev, format, ## arg) 49 #define tb_ctl_warn(ctl, format, arg...) \ 50 dev_warn(&(ctl)->nhi->pdev->dev, format, ## arg) 52 #define tb_ctl_info(ctl, format, arg...) \ 53 dev_info(&(ctl) 237 tb_cfg_print_error(struct tb_ctl *ctl, const struct tb_cfg_result *res) argument 304 tb_ctl_pkg_alloc(struct tb_ctl *ctl) argument 336 tb_ctl_tx(struct tb_ctl *ctl, void *data, size_t len, enum tb_cfg_pkg_type type) argument 369 tb_ctl_handle_plug_event(struct tb_ctl *ctl, struct ctl_pkg *response) argument 440 tb_ctl_rx(struct tb_ctl *ctl, void *buffer, size_t length, int timeout_msec, u64 route, enum tb_cfg_pkg_type type) argument 477 struct tb_ctl *ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); local 520 tb_ctl_free(struct tb_ctl *ctl) argument 541 tb_ctl_start(struct tb_ctl *ctl) argument 559 tb_ctl_stop(struct tb_ctl *ctl) argument 577 tb_cfg_error(struct tb_ctl *ctl, u64 route, u32 port, enum tb_cfg_error error) argument 596 tb_cfg_reset(struct tb_ctl *ctl, u64 route, int timeout_msec) argument 616 tb_cfg_read_raw(struct tb_ctl *ctl, void *buffer, u64 route, u32 port, enum tb_cfg_space space, u32 offset, u32 length, int timeout_msec) argument 653 tb_cfg_write_raw(struct tb_ctl *ctl, void *buffer, u64 route, u32 port, enum tb_cfg_space space, u32 offset, u32 length, int timeout_msec) argument 685 tb_cfg_read(struct tb_ctl *ctl, void *buffer, u64 route, u32 port, enum tb_cfg_space space, u32 offset, u32 length) argument 698 tb_cfg_write(struct tb_ctl *ctl, void *buffer, u64 route, u32 port, enum tb_cfg_space space, u32 offset, u32 length) argument 720 tb_cfg_get_upstream_port(struct tb_ctl *ctl, u64 route) argument [all...] |
H A D | ctl.h | 18 void tb_ctl_start(struct tb_ctl *ctl); 19 void tb_ctl_stop(struct tb_ctl *ctl); 20 void tb_ctl_free(struct tb_ctl *ctl); 56 int tb_cfg_error(struct tb_ctl *ctl, u64 route, u32 port, 58 struct tb_cfg_result tb_cfg_reset(struct tb_ctl *ctl, u64 route, 60 struct tb_cfg_result tb_cfg_read_raw(struct tb_ctl *ctl, void *buffer, 64 struct tb_cfg_result tb_cfg_write_raw(struct tb_ctl *ctl, void *buffer, 68 int tb_cfg_read(struct tb_ctl *ctl, void *buffer, u64 route, u32 port, 70 int tb_cfg_write(struct tb_ctl *ctl, void *buffer, u64 route, u32 port, 72 int tb_cfg_get_upstream_port(struct tb_ctl *ctl, u6 [all...] |
H A D | eeprom.c | 14 static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) argument 16 return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1); 22 static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) argument 24 return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1); 40 struct tb_eeprom_ctl ctl; local 41 int res = tb_eeprom_ctl_read(sw, &ctl); 45 ctl.access_high = 1; 46 res = tb_eeprom_ctl_write(sw, &ctl); 49 ctl.access_low = 0; 50 return tb_eeprom_ctl_write(sw, &ctl); 67 tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl, enum tb_eeprom_transfer direction) argument 94 struct tb_eeprom_ctl ctl; local 114 struct tb_eeprom_ctl ctl; local [all...] |
H A D | Makefile | 2 thunderbolt-objs := nhi.o ctl.o tb.o switch.o cap.o path.o tunnel_pci.o eeprom.o
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/drivers/ide/ |
H A D | ide-legacy.c | 9 unsigned long base, ctl; local 14 ctl = 0x3f6; 18 ctl = 0x376; 28 if (!request_region(ctl, 1, d->name)) { 30 d->name, ctl); 35 ide_std_init_ports(hw, base, ctl);
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H A D | ide-pnp.c | 39 unsigned long base, ctl; local 49 ctl = pnp_port_start(dev, 1); 57 if (!request_region(ctl, 1, DRV_NAME)) { 59 DRV_NAME, ctl); 65 ide_std_init_ports(&hw, base, ctl); 76 release_region(ctl, 1);
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H A D | ide-4drives.c | 33 unsigned long base = 0x1f0, ctl = 0x3f6; local 45 if (!request_region(ctl, 1, DRV_NAME)) { 47 DRV_NAME, ctl); 54 ide_std_init_ports(&hw, base, ctl);
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H A D | buddha.c | 122 unsigned long ctl, unsigned long irq_port) 133 hw->io_ports.ctl_addr = ctl; 212 unsigned long base, ctl, irq_port; local 216 ctl = base + BUDDHA_CONTROL; 221 ctl = 0; 225 buddha_setup_ports(&hw[i], base, ctl, irq_port); 121 buddha_setup_ports(struct ide_hw *hw, unsigned long base, unsigned long ctl, unsigned long irq_port) argument
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H A D | tx4939ide.c | 152 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); local 154 if (ctl & TX4939IDE_INT_BUSERR) { 164 if (ctl & (TX4939IDE_INT_ADDRERR | 167 hwif->name, ctl, 168 ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "", 169 ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "", 170 ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : ""); 171 return ctl; 178 u16 ctl; local 188 ctl 320 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); local 347 u16 ctl, ide_int; local [all...] |
/drivers/net/wireless/ath/wcn36xx/ |
H A D | dxe.c | 66 struct wcn36xx_dxe_ctl *ctl = ch->head_blk_ctl, *next; local 69 for (i = 0; i < ch->desc_num && ctl; i++) { 70 next = ctl->next; 71 kfree(ctl); 72 ctl = next; 272 static int wcn36xx_dxe_fill_skb(struct wcn36xx_dxe_ctl *ctl) argument 274 struct wcn36xx_dxe_desc *dxe = ctl->desc; 285 ctl->skb = skb; 347 struct wcn36xx_dxe_ctl *ctl = ch->tail_blk_ctl; local 357 if (ctl 466 struct wcn36xx_dxe_ctl *ctl = ch->head_blk_ctl; local 592 struct wcn36xx_dxe_ctl *ctl = NULL; local [all...] |
/drivers/net/ethernet/chelsio/cxgb/ |
H A D | mv88e1xxx.c | 49 u32 ctl; local 55 (void) simple_mdio_read(cphy, MII_BMCR, &ctl); 56 ctl &= BMCR_RESET; 57 if (ctl) 59 } while (ctl && --time_out); 61 return ctl ? -1 : 0; 126 u32 ctl; local 128 (void) simple_mdio_read(phy, MII_BMCR, &ctl); 130 ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE); 132 ctl | 162 u32 ctl; local 175 u32 ctl; local [all...] |
/drivers/char/hw_random/ |
H A D | octeon-rng.c | 30 union cvmx_rnm_ctl_status ctl; local 33 ctl.u64 = 0; 34 ctl.s.ent_en = 1; /* Enable the entropy source. */ 35 ctl.s.rng_en = 1; /* Enable the RNG hardware. */ 36 cvmx_write_csr((u64)p->control_status, ctl.u64); 42 union cvmx_rnm_ctl_status ctl; local 45 ctl.u64 = 0; 47 cvmx_write_csr((u64)p->control_status, ctl.u64);
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H A D | pasemi-rng.c | 71 u32 ctl; local 73 ctl = SDCRNG_CTL_DR | SDCRNG_CTL_SELECT_RRG_RNG | SDCRNG_CTL_KSZ; 74 out_le32(rng_regs + SDCRNG_CTL_REG, ctl); 75 out_le32(rng_regs + SDCRNG_CTL_REG, ctl & ~SDCRNG_CTL_DR); 83 u32 ctl; local 85 ctl = SDCRNG_CTL_RE | SDCRNG_CTL_CE; 87 in_le32(rng_regs + SDCRNG_CTL_REG) & ~ctl);
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/drivers/video/fbdev/ |
H A D | n411.c | 46 static unsigned char ctl; variable 54 ctl &= ~(HCB_CD_BIT); 56 ctl |= HCB_CD_BIT; 60 ctl &= ~(HCB_DS_BIT); 62 ctl |= HCB_DS_BIT; 65 outb(ctl, cio_addr); 107 ctl = HCB_WUP_BIT | HCB_RW_BIT | HCB_CD_BIT ;
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/drivers/net/ethernet/apm/xgene/ |
H A D | xgene_enet_sgmac.c | 42 static bool xgene_enet_wr_indirect(struct xgene_indirect_ctl *ctl, argument 47 iowrite32(wr_addr, ctl->addr); 48 iowrite32(wr_data, ctl->ctl); 49 iowrite32(XGENE_ENET_WR_CMD, ctl->cmd); 53 if (ioread32(ctl->cmd_done)) { 54 iowrite32(0, ctl->cmd); 66 struct xgene_indirect_ctl ctl = { local 68 .ctl = p->mcx_mac_addr + MAC_WRITE_REG_OFFSET, 73 if (!xgene_enet_wr_indirect(&ctl, wr_add 87 xgene_enet_rd_indirect(struct xgene_indirect_ctl *ctl, u32 rd_addr) argument 113 struct xgene_indirect_ctl ctl = { local [all...] |
/drivers/net/phy/ |
H A D | et1011c.c | 54 int ctl = 0; local 55 ctl = phy_read(phydev, MII_BMCR); 56 if (ctl < 0) 57 return ctl; 58 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | 61 phy_write(phydev, MII_BMCR, ctl | BMCR_RESET);
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/drivers/net/wireless/b43/ |
H A D | pio.c | 331 u16 ctl, 339 ctl |= B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_WRITEHI; 340 b43_piotx_write16(q, B43_PIO_TXCTL, ctl); 350 ctl &= ~B43_PIO_TXCTL_WRITEHI; 351 b43_piotx_write16(q, B43_PIO_TXCTL, ctl); 359 return ctl; 368 u16 ctl; local 370 ctl = b43_piotx_read16(q, B43_PIO_TXCTL); 371 ctl |= B43_PIO_TXCTL_FREADY; 372 ctl 330 tx_write_2byte_queue(struct b43_pio_txqueue *q, u16 ctl, const void *_data, unsigned int data_len) argument 383 tx_write_4byte_queue(struct b43_pio_txqueue *q, u32 ctl, const void *_data, unsigned int data_len) argument 438 u32 ctl; local 636 u32 ctl; local 650 u16 ctl; local [all...] |
/drivers/isdn/mISDN/ |
H A D | clock.c | 18 * ctl = callback function to enable/disable clock source 22 * Note: Callback 'ctl' can be called before mISDN_register_clock returns! 78 lastclock->ctl(lastclock->priv, 0); 85 bestclock->ctl(bestclock->priv, 1); 95 *mISDN_register_clock(char *name, int pri, clockctl_func_t *ctl, void *priv) argument 110 iclock->ctl = ctl; 133 iclock->ctl(iclock->priv, 0); 155 iclock->ctl(iclock->priv, 0);
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/drivers/net/ethernet/ibm/emac/ |
H A D | phy.c | 111 int ctl, adv; local 119 ctl = phy_read(phy, MII_BMCR); 120 if (ctl < 0) 121 return ctl; 122 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE); 125 phy_write(phy, MII_BMCR, ctl); 161 ctl = phy_read(phy, MII_BMCR); 162 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); 163 phy_write(phy, MII_BMCR, ctl); 170 int ctl; local [all...] |
/drivers/net/wireless/b43legacy/ |
H A D | leds.c | 39 u16 ctl; local 42 ctl = b43legacy_read16(dev, B43legacy_MMIO_GPIO_CONTROL); 44 ctl &= ~(1 << led_index); 46 ctl |= (1 << led_index); 47 b43legacy_write16(dev, B43legacy_MMIO_GPIO_CONTROL, ctl); 56 u16 ctl; local 59 ctl = b43legacy_read16(dev, B43legacy_MMIO_GPIO_CONTROL); 61 ctl |= (1 << led_index); 63 ctl &= ~(1 << led_index); 64 b43legacy_write16(dev, B43legacy_MMIO_GPIO_CONTROL, ctl); [all...] |
/drivers/mmc/host/ |
H A D | tmio_mmc.h | 44 void __iomem *ctl; member in struct:tmio_mmc_host 154 return readw(host->ctl + (addr << host->pdata->bus_shift)); 160 readsw(host->ctl + (addr << host->pdata->bus_shift), buf, count); 165 return readw(host->ctl + (addr << host->pdata->bus_shift)) | 166 readw(host->ctl + ((addr + 2) << host->pdata->bus_shift)) << 16; 176 writew(val, host->ctl + (addr << host->pdata->bus_shift)); 182 writesw(host->ctl + (addr << host->pdata->bus_shift), buf, count); 187 writew(val, host->ctl + (addr << host->pdata->bus_shift)); 188 writew(val >> 16, host->ctl + ((addr + 2) << host->pdata->bus_shift));
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/drivers/net/wireless/ath/ath9k/ |
H A D | ar9003_wow.c | 59 u32 ctl[13] = {0}; local 68 ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16)); 69 ctl[1] = 0; 70 ctl[3] = 0xb; /* OFDM_6M hardware value for this rate */ 71 ctl[4] = 0; 72 ctl[7] = (ah->txchainmask) << 2; 73 ctl[2] = 0xf << 16; /* tx_tries 0 */ 76 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); 78 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
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/drivers/net/ |
H A D | sungem_phy.c | 315 u16 ctl, adv; local 337 ctl = sungem_phy_read(phy, MII_BMCR); 338 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); 339 sungem_phy_write(phy, MII_BMCR, ctl); 346 u16 ctl; local 353 ctl = sungem_phy_read(phy, MII_BMCR); 354 ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_ANENABLE); 357 sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET); 364 ctl |= BMCR_SPEED100; 371 ctl | 470 u16 ctl, adv; local 514 u16 ctl; local 746 u16 ctl, adv; local 797 u16 ctl, ctl2; local [all...] |
/drivers/rtc/ |
H A D | rtc-tx4939.c | 34 __raw_writel(cmd, &rtcreg->ctl); 36 while (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_BUSY) { 64 (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); 80 (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); 133 u32 ctl; local 138 (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); 146 ctl = __raw_readl(&rtcreg->ctl); 147 alrm->enabled = (ctl & TX4939_RTCCTL_ALME) ? 1 : 0; 148 alrm->pending = (ctl [all...] |
/drivers/i2c/busses/ |
H A D | i2c-pnx.c | 285 u32 ctl = 0; local 311 ctl = ioread32(I2C_REG_CTL(alg_data)); 312 ctl |= mcntrl_rffie | mcntrl_daie; 313 ctl &= ~mcntrl_drmie; 314 iowrite32(ctl, I2C_REG_CTL(alg_data)); 344 ctl = ioread32(I2C_REG_CTL(alg_data)); 345 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | 347 iowrite32(ctl, I2C_REG_CTL(alg_data)); 364 u32 stat, ctl; local 380 ctl 441 u32 ctl; local [all...] |