Searched refs:div_reg (Results 1 - 5 of 5) sorted by relevance
| /drivers/clk/socfpga/ |
| H A D | clk-periph.c | 37 if (socfpgaclk->div_reg) {
38 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
63 u32 div_reg[3]; local
73 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
75 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];
76 periph_clk->shift = div_reg[1];
77 periph_clk->width = div_reg[2];
79 periph_clk->div_reg = 0;
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| H A D | clk.h | 46 void __iomem *div_reg; member in struct:socfpga_gate_clk
47 u32 width; /* only valid if div_reg != 0 */
48 u32 shift; /* only valid if div_reg != 0 */
56 void __iomem *div_reg; member in struct:socfpga_periph_clk
57 u32 width; /* only valid if div_reg != 0 */
58 u32 shift; /* only valid if div_reg != 0 */
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| H A D | clk-gate.c | 111 else if (socfpgaclk->div_reg) {
112 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
115 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
188 u32 div_reg[3]; local
221 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
223 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
224 socfpga_clk->shift = div_reg[1];
225 socfpga_clk->width = div_reg[2];
227 socfpga_clk->div_reg
[all...] |
| /drivers/clk/ |
| H A D | clk-vt8500.c | 31 void __iomem *div_reg; member in struct:clk_device
127 u32 div = readl(cdev->div_reg) & cdev->div_mask;
198 writel(divisor, cdev->div_reg);
234 u32 en_reg, div_reg; local
264 rc = of_property_read_u32(node, "divisor-reg", &div_reg);
266 dev_clk->div_reg = pmc_base + div_reg;
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| /drivers/clk/hisilicon/ |
| H A D | clk-hi3620.c | 242 u32 div_reg; member in struct:hisi_mmc_clock
258 void __iomem *div_reg; member in struct:clk_mmc
391 val = readl_relaxed(mclk->div_reg);
393 writel_relaxed(val, mclk->div_reg);
453 mclk->div_reg = base + mmc_clk->div_reg;
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