Searched refs:fp_horiz_regs (Results 1 - 5 of 5) sorted by last modified time

/drivers/gpu/drm/nouveau/dispnv04/
H A Ddfp.c299 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
300 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
304 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
306 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1;
307 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
308 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
309 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
310 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
394 regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
395 regp->fp_horiz_regs[FP_VALID_EN
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H A Ddisp.h51 uint32_t fp_horiz_regs[7]; member in struct:nv04_crtc_reg
H A Dhw.c423 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
501 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
H A Dtvmodesnv17.c573 regs->fp_horiz_regs[FP_VALID_START] = hmargin;
574 regs->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - hmargin - 1;
584 regs->fp_horiz_regs[FP_VALID_START]);
586 regs->fp_horiz_regs[FP_VALID_END]);
H A Dtvnv17.c541 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
542 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
543 regs->fp_horiz_regs[FP_SYNC_START] =
545 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
546 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +

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