Searched refs:fp_vert_regs (Results 1 - 5 of 5) sorted by last modified time

/drivers/gpu/drm/nouveau/dispnv04/
H A Ddfp.c312 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
313 regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
314 regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
315 regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
316 regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
317 regp->fp_vert_regs[FP_VALID_START] = 0;
318 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
410 regp->fp_vert_regs[FP_VALID_START] += diff / 2;
411 regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
H A Ddisp.h52 uint32_t fp_vert_regs[7]; member in struct:nv04_crtc_reg
H A Dhw.c422 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
500 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
H A Dtvmodesnv17.c575 regs->fp_vert_regs[FP_VALID_START] = vmargin;
576 regs->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - vmargin - 1;
588 regs->fp_vert_regs[FP_VALID_START]);
590 regs->fp_vert_regs[FP_VALID_END]);
H A Dtvnv17.c549 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
550 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
551 regs->fp_vert_regs[FP_SYNC_START] =
553 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
554 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;

Completed in 27 milliseconds