Searched refs:head (Results 1 - 25 of 857) sorted by relevance

1234567891011>>

/drivers/scsi/aic7xxx/
H A Dqueue.h40 * added to the list after an existing element or at the head of the list.
41 * Elements being removed from the head of the list should use the explicit
48 * head of the list and the other to the tail of the list. The elements are
51 * to the list after an existing element, at the head of the list, or at the
52 * end of the list. Elements being removed from the head of the tail queue
62 * or after an existing element or at the head of the list. A list
65 * A tail queue is headed by a pair of pointers, one to the head of the
69 * after an existing element, at the head of the list, or at the end of
72 * A circle queue is headed by a pair of pointers, one to the head of the
76 * an existing element, at the head o
[all...]
/drivers/infiniband/hw/amso1100/
H A Dc2_alloc.c40 struct sp_chunk **head)
55 new_head->head = 0;
67 *head = new_head;
89 __be16 *c2_alloc_mqsp(struct c2_dev *c2dev, struct sp_chunk *head, argument
94 while (head) {
95 mqsp = head->head;
97 head->head = head
39 c2_alloc_mqsp_chunk(struct c2_dev *c2dev, gfp_t gfp_mask, struct sp_chunk **head) argument
124 struct sp_chunk *head; local
[all...]
/drivers/scsi/sym53c8xx_2/
H A Dsym_misc.h55 static inline struct sym_quehead *sym_que_first(struct sym_quehead *head) argument
57 return (head->flink == head) ? 0 : head->flink;
60 static inline struct sym_quehead *sym_que_last(struct sym_quehead *head) argument
62 return (head->blink == head) ? 0 : head->blink;
82 static inline int sym_que_empty(struct sym_quehead *head) argument
84 return head
87 sym_que_splice(struct sym_quehead *list, struct sym_quehead *head) argument
132 sym_remque_head(struct sym_quehead *head) argument
145 sym_remque_tail(struct sym_quehead *head) argument
[all...]
/drivers/net/wireless/ath/carl9170/
H A Dfwdesc.h119 struct carl9170fw_desc_head head; member in struct:carl9170fw_otus_desc
140 struct carl9170fw_desc_head head; member in struct:carl9170fw_motd_desc
157 struct carl9170fw_desc_head head; member in struct:carl9170fw_fix_desc
166 struct carl9170fw_desc_head head; member in struct:carl9170fw_dbg_desc
182 struct carl9170fw_desc_head head; member in struct:carl9170fw_chk_desc
192 struct carl9170fw_desc_head head; member in struct:carl9170fw_txsq_desc
202 struct carl9170fw_desc_head head; member in struct:carl9170fw_wol_desc
212 struct carl9170fw_desc_head head; member in struct:carl9170fw_last_desc
220 .head = { \
227 static inline void carl9170fw_fill_desc(struct carl9170fw_desc_head *head, argument
256 carl9170fw_desc_cmp(const struct carl9170fw_desc_head *head, const u8 descid[CARL9170FW_MAGIC_SIZE], u16 min_len, u8 compatible_revision) argument
[all...]
/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.h38 void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value);
39 uint8_t NVReadVgaSeq(struct drm_device *, int head, uint8_t index);
40 void NVWriteVgaGr(struct drm_device *, int head, uint8_t index, uint8_t value);
41 uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index);
43 void NVBlankScreen(struct drm_device *, int head, bool blank);
49 void nouveau_hw_save_state(struct drm_device *, int head,
51 void nouveau_hw_load_state(struct drm_device *, int head,
53 void nouveau_hw_load_state_palette(struct drm_device *, int head,
61 int head, uint32_t reg)
65 if (head)
60 NVReadCRTC(struct drm_device *dev, int head, uint32_t reg) argument
71 NVWriteCRTC(struct drm_device *dev, int head, uint32_t reg, uint32_t val) argument
80 NVReadRAMDAC(struct drm_device *dev, int head, uint32_t reg) argument
91 NVWriteRAMDAC(struct drm_device *dev, int head, uint32_t reg, uint32_t val) argument
120 NVWriteVgaCrtc(struct drm_device *dev, int head, uint8_t index, uint8_t value) argument
128 NVReadVgaCrtc(struct drm_device *dev, int head, uint8_t index) argument
153 NVWriteVgaCrtc5758(struct drm_device *dev, int head, uint8_t index, uint8_t value) argument
159 NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_t index) argument
165 NVReadPRMVIO(struct drm_device *dev, int head, uint32_t reg) argument
181 NVWritePRMVIO(struct drm_device *dev, int head, uint32_t reg, uint8_t value) argument
195 NVSetEnablePalette(struct drm_device *dev, int head, bool enable) argument
202 NVGetEnablePalette(struct drm_device *dev, int head) argument
209 NVWriteVgaAttr(struct drm_device *dev, int head, uint8_t index, uint8_t value) argument
223 NVReadVgaAttr(struct drm_device *dev, int head, uint8_t index) argument
239 NVVgaSeqReset(struct drm_device *dev, int head, bool start) argument
244 NVVgaProtect(struct drm_device *dev, int head, bool protect) argument
273 nv_lock_vga_crtc_base(struct drm_device *dev, int head, bool lock) argument
288 nv_lock_vga_crtc_shadow(struct drm_device *dev, int head, int lock) argument
342 nv_fix_nv40_hw_cursor(struct drm_device *dev, int head) argument
354 nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset) argument
373 nv_show_cursor(struct drm_device *dev, int head, bool show) argument
[all...]
H A Dhw.c39 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) argument
41 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
42 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value);
46 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) argument
48 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
49 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR);
53 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) argument
55 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
56 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value);
60 NVReadVgaGr(struct drm_device *dev, int head, uint8_ argument
110 NVBlankScreen(struct drm_device *dev, int head, bool blank) argument
246 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) argument
373 rd_cio_state(struct drm_device *dev, int head, struct nv04_crtc_reg *crtcstate, int index) argument
380 wr_cio_state(struct drm_device *dev, int head, struct nv04_crtc_reg *crtcstate, int index) argument
387 nv_save_state_ramdac(struct drm_device *dev, int head, struct nv04_mode_state *state) argument
462 nv_load_state_ramdac(struct drm_device *dev, int head, struct nv04_mode_state *state) argument
534 nv_save_state_vga(struct drm_device *dev, int head, struct nv04_mode_state *state) argument
558 nv_load_state_vga(struct drm_device *dev, int head, struct nv04_mode_state *state) argument
584 nv_save_state_ext(struct drm_device *dev, int head, struct nv04_mode_state *state) argument
659 nv_load_state_ext(struct drm_device *dev, int head, struct nv04_mode_state *state) argument
765 nv_save_state_palette(struct drm_device *dev, int head, struct nv04_mode_state *state) argument
784 nouveau_hw_load_state_palette(struct drm_device *dev, int head, struct nv04_mode_state *state) argument
802 nouveau_hw_save_state(struct drm_device *dev, int head, struct nv04_mode_state *state) argument
816 nouveau_hw_load_state(struct drm_device *dev, int head, struct nv04_mode_state *state) argument
[all...]
/drivers/gpu/drm/nouveau/nvif/
H A Dlist.h45 * We need one list head in bar and a list element in all list_of_foos (both are of
60 * Now we initialize the list head:
102 * to-be-linked struct. struct list_head is required for both the head of the
107 * There are no requirements for a list head, any struct list_head can be a list
108 * head.
144 * Insert a new element after the given list head. The new element does not
147 * head → some element → ...
149 * head → new element → older element → ...
156 * @param head The existing list.
159 list_add(struct list_head *entry, struct list_head *head) argument
180 list_add_tail(struct list_head *entry, struct list_head *head) argument
219 list_move_tail(struct list_head *list, struct list_head *head) argument
235 list_empty(struct list_head *head) argument
[all...]
/drivers/gpu/drm/nouveau/core/include/subdev/
H A Dvga.h7 u8 nv_rdport(void *obj, int head, u16 port);
8 void nv_wrport(void *obj, int head, u16 port, u8 value);
11 u8 nv_rdvgas(void *obj, int head, u8 index);
12 void nv_wrvgas(void *obj, int head, u8 index, u8 value);
15 u8 nv_rdvgag(void *obj, int head, u8 index);
16 void nv_wrvgag(void *obj, int head, u8 index, u8 value);
19 u8 nv_rdvgac(void *obj, int head, u8 index);
20 void nv_wrvgac(void *obj, int head, u8 index, u8 value);
23 u8 nv_rdvgai(void *obj, int head, u16 port, u8 index);
24 void nv_wrvgai(void *obj, int head, u1
[all...]
/drivers/staging/lustre/lustre/ptlrpc/
H A Dnrs_fifo.c39 * enabled on a given NRS head.
81 struct nrs_fifo_head *head; local
83 OBD_CPT_ALLOC_PTR(head, nrs_pol2cptab(policy), nrs_pol2cptid(policy));
84 if (head == NULL)
87 INIT_LIST_HEAD(&head->fh_list);
88 policy->pol_private = head;
103 struct nrs_fifo_head *head = policy->pol_private; local
105 LASSERT(head != NULL);
106 LASSERT(list_empty(&head->fh_list));
108 OBD_FREE_PTR(head);
163 struct nrs_fifo_head *head = policy->pol_private; local
197 struct nrs_fifo_head *head; local
[all...]
/drivers/gpu/drm/nouveau/core/engine/disp/
H A Dvga.c30 nv_rdport(void *obj, int head, u16 port) argument
40 return nv_rd08(obj, 0x601000 + (head * 0x2000) + port);
46 head = 0; /* CR44 selects head */
47 return nv_rd08(obj, 0x0c0000 + (head * 0x2000) + port);
55 nv_wrport(void *obj, int head, u16 port, u8 data) argument
65 nv_wr08(obj, 0x601000 + (head * 0x2000) + port, data);
71 head = 0; /* CR44 selects head */
72 nv_wr08(obj, 0x0c0000 + (head *
78 nv_rdvgas(void *obj, int head, u8 index) argument
85 nv_wrvgas(void *obj, int head, u8 index, u8 value) argument
92 nv_rdvgag(void *obj, int head, u8 index) argument
99 nv_wrvgag(void *obj, int head, u8 index, u8 value) argument
106 nv_rdvgac(void *obj, int head, u8 index) argument
113 nv_wrvgac(void *obj, int head, u8 index, u8 value) argument
120 nv_rdvgai(void *obj, int head, u16 port, u8 index) argument
130 nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value) argument
[all...]
H A Dnvd0.c629 const u32 total = nv_rd32(priv, 0x640414 + (head * 0x300));
630 const u32 blanke = nv_rd32(priv, 0x64041c + (head * 0x300));
631 const u32 blanks = nv_rd32(priv, 0x640420 + (head * 0x300));
648 nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff;
651 nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff;
676 for (i = 0; i < priv->head.nr; i++) {
721 for (i = 0; i < priv->head.nr; i++)
770 nvd0_disp_vblank_init(struct nvkm_event *event, int type, int head) argument
773 nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001);
777 nvd0_disp_vblank_fini(struct nvkm_event *event, int type, int head) argument
791 exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *info) argument
837 exec_script(struct nv50_disp_priv *priv, int head, int id) argument
873 exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) argument
935 nvd0_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head) argument
941 nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head) argument
963 nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head) argument
973 nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head, struct dcb_output *outp) argument
1034 nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) argument
1076 nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head) argument
1091 int head; local
[all...]
/drivers/gpu/drm/radeon/
H A Dmkregtable.c79 * @head: list head to add it after
81 * Insert a new entry after the specified head.
84 static inline void list_add(struct list_head *new, struct list_head *head) argument
86 __list_add(new, head, head->next);
92 * @head: list head to add it before
94 * Insert a new entry before the specified head.
97 static inline void list_add_tail(struct list_head *new, struct list_head *head) argument
169 list_move(struct list_head *list, struct list_head *head) argument
180 list_move_tail(struct list_head *list, struct list_head *head) argument
192 list_is_last(const struct list_head *list, const struct list_head *head) argument
202 list_empty(const struct list_head *head) argument
220 list_empty_careful(const struct list_head *head) argument
230 list_is_singular(const struct list_head *head) argument
235 __list_cut_position(struct list_head *list, struct list_head *head, struct list_head *entry) argument
262 list_cut_position(struct list_head *list, struct list_head *head, struct list_head *entry) argument
294 list_splice(const struct list_head *list, struct list_head *head) argument
306 list_splice_tail(struct list_head *list, struct list_head *head) argument
320 list_splice_init(struct list_head *list, struct list_head *head) argument
337 list_splice_tail_init(struct list_head *list, struct list_head *head) argument
[all...]
/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_marker.c32 struct list_head head; member in struct:vmw_marker
39 INIT_LIST_HEAD(&queue->head);
50 list_for_each_entry_safe(marker, next, &queue->head, head) {
67 list_add_tail(&marker->head, &queue->head);
83 if (list_empty(&queue->head)) {
90 list_for_each_entry_safe(marker, next, &queue->head, head) {
97 list_del(&marker->head);
[all...]
H A Dvmwgfx_cmdbuf_res.c43 * @head: List head used either by the staging list or the manager list
51 struct list_head head; member in struct:vmw_cmdbuf_res
113 list_del(&entry->head);
133 list_for_each_entry_safe(entry, next, list, head) {
134 list_del(&entry->head);
138 list_add_tail(&entry->head, &entry->man->list);
168 list_for_each_entry_safe(entry, next, list, head) {
176 list_del(&entry->head);
177 list_add_tail(&entry->head,
[all...]
/drivers/gpu/drm/nouveau/
H A Dnv10_fence.h10 struct nvif_object head[4]; member in struct:nv10_fence_chan
H A Dnv50_display.h43 struct nouveau_bo *nv50_display_crtc_sema(struct drm_device *, int head);
/drivers/staging/android/fiq_debugger/
H A Dfiq_debugger_ringbuf.h23 int head; member in struct:fiq_debugger_ringbuf
38 rbuf->head = 0;
52 int level = rbuf->head - rbuf->tail;
88 rbuf->buf[rbuf->head] = datum;
90 rbuf->head = (rbuf->head + 1) % rbuf->len;
/drivers/staging/unisys/channels/
H A Dchannel.c50 unsigned int head, tail, nof; local
57 /* capture current head and tail */
58 head = readl(&pqhdr->Head);
61 /* queue is full if (head + 1) % n equals tail */
62 if (((head + 1) % readl(&pqhdr->MaxSignalSlots)) == tail) {
68 /* increment the head index */
69 head = (head + 1) % readl(&pqhdr->MaxSignalSlots);
71 /* copy signal to the head location from the area pointed to
75 (head * read
108 unsigned int head, tail; local
163 unsigned int head, tail, signalCount = 0; local
[all...]
/drivers/gpu/drm/
H A Ddrm_agpsupport.c222 list_add(&entry->head, &dev->agp->memory);
254 list_for_each_entry(entry, &dev->agp->memory, head) {
369 list_del(&entry->head);
401 struct drm_agp_head *head = NULL; local
403 if (!(head = kzalloc(sizeof(*head), GFP_KERNEL)))
405 head->bridge = agp_find_bridge(dev->pdev);
406 if (!head->bridge) {
407 if (!(head->bridge = agp_backend_acquire(dev->pdev))) {
408 kfree(head);
[all...]
H A Ddrm_hashtab.c69 hlist_for_each_entry(entry, h_list, head)
82 hlist_for_each_entry(entry, h_list, head) {
84 return &entry->head;
100 hlist_for_each_entry_rcu(entry, h_list, head) {
102 return &entry->head;
120 hlist_for_each_entry(entry, h_list, head) {
125 parent = &entry->head;
128 hlist_add_behind_rcu(&item->head, parent);
130 hlist_add_head_rcu(&item->head, h_list);
174 *item = hlist_entry(list, struct drm_hash_item, head);
[all...]
/drivers/net/wireless/ath/
H A Ddfs_pri_detector.c34 struct list_head head; member in struct:pulse_elem
102 list_for_each_entry_safe(p, p0, &pulse_pool, head) {
103 list_del(&p->head);
107 list_for_each_entry_safe(ps, ps0, &pseq_pool, head) {
108 list_del(&ps->head);
119 list_add(&pe->head, &pulse_pool);
127 list_add(&pse->head, &pseq_pool);
137 pse = list_first_entry(&pseq_pool, struct pri_sequence, head);
138 list_del(&pse->head);
150 pe = list_first_entry(&pulse_pool, struct pulse_elem, head);
[all...]
/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_mbx.c33 fifo->head = 0;
45 return fifo->tail - fifo->head;
56 return fifo->size + fifo->head - fifo->tail;
67 return fifo->head == fifo->tail;
71 * fm10k_fifo_head_offset - returns indices of head with given offset
73 * @offset: offset to add to head
75 * This function returns the indicies into the fifo based on head + offset
79 return (fifo->head + offset) & (fifo->size - 1);
102 u32 *head = fifo->buffer + fm10k_fifo_head_offset(fifo, 0); local
104 /* verify there is at least 1 DWORD in the fifo so *head i
137 fm10k_mbx_index_len(struct fm10k_mbx_info *mbx, u16 head, u16 tail) argument
190 u16 head = (mbx->head + offset + 1) & ((mbx->mbmem_len << 1) - 1); local
206 u16 head = (mbx->head - offset - 1) & ((mbx->mbmem_len << 1) - 1); local
339 u32 *head = fifo->buffer; local
384 fm10k_mbx_pull_head(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx, u16 head) argument
431 u16 end, len, head; local
617 fm10k_mbx_update_local_crc(struct fm10k_mbx_info *mbx, u16 head) argument
932 u16 type, rsvd0, head, tail, size; local
996 fm10k_mbx_create_reply(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx, u16 head) argument
1110 u16 size, head; local
1155 u16 head, tail; local
1197 u16 head, tail; local
1250 u16 head; local
1734 u16 tail, head, ver; local
1875 fm10k_sm_mbx_transmit(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx, u16 head) argument
1918 fm10k_sm_mbx_create_reply(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx, u16 head) argument
1993 u16 head, tail; local
[all...]
/drivers/infiniband/hw/ipath/
H A Dipath_cq.c52 u32 head; local
58 * Note that the head pointer might be writable by user processes.
62 head = wc->head;
63 if (head >= (unsigned) cq->ibcq.cqe) {
64 head = cq->ibcq.cqe;
67 next = head + 1;
81 wc->uqueue[head].wr_id = entry->wr_id;
82 wc->uqueue[head].status = entry->status;
83 wc->uqueue[head]
376 u32 head, tail, n; local
[all...]
/drivers/infiniband/hw/qib/
H A Dqib_cq.c55 u32 head; local
61 * Note that the head pointer might be writable by user processes.
65 head = wc->head;
66 if (head >= (unsigned) cq->ibcq.cqe) {
67 head = cq->ibcq.cqe;
70 next = head + 1;
84 wc->uqueue[head].wr_id = entry->wr_id;
85 wc->uqueue[head].status = entry->status;
86 wc->uqueue[head]
392 u32 head, tail, n; local
[all...]
/drivers/dma/
H A Dvirt-dma.h44 void vchan_dma_desc_free_list(struct virt_dma_chan *vc, struct list_head *head);
127 * head: list of descriptors found
135 struct list_head *head)
137 list_splice_tail_init(&vc->desc_submitted, head);
138 list_splice_tail_init(&vc->desc_issued, head);
139 list_splice_tail_init(&vc->desc_completed, head);
145 LIST_HEAD(head);
148 vchan_get_all_descriptors(vc, &head);
151 vchan_dma_desc_free_list(vc, &head);
134 vchan_get_all_descriptors(struct virt_dma_chan *vc, struct list_head *head) argument

Completed in 6487 milliseconds

1234567891011>>