Searched refs:impl (Results 1 - 25 of 26) sorted by relevance

12

/drivers/gpu/drm/nouveau/core/subdev/devinit/
H A Dbase.c51 struct nouveau_devinit_impl *impl = (void *)object->oclass; local
63 if (impl->disable)
64 nv_device(devinit)->disable_mask |= impl->disable(devinit);
85 struct nouveau_devinit_impl *impl = (void *)oclass; local
97 devinit->meminit = impl->meminit;
98 devinit->pll_set = impl->pll_set;
99 devinit->mmio = impl->mmio;
/drivers/gpu/drm/nouveau/core/subdev/fb/
H A Dnv04.c61 struct nv04_fb_impl *impl = (void *)oclass; local
70 priv->base.tile.regions = impl->tile.regions;
71 priv->base.tile.init = impl->tile.init;
72 priv->base.tile.comp = impl->tile.comp;
73 priv->base.tile.fini = impl->tile.fini;
74 priv->base.tile.prog = impl->tile.prog;
H A Dbase.c112 struct nouveau_fb_impl *impl = (void *)oclass; local
136 pfb->memtype_valid = impl->memtype;
139 impl->ram, NULL, 0, &ram);
H A Dnv50.c284 struct nv50_fb_impl *impl = (void *)object->oclass; local
300 nv_wr32(priv, 0x100c90, impl->trap);
/drivers/gpu/drm/nouveau/core/subdev/ltc/
H A Dbase.c51 const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); local
57 impl->cbc_clear(priv, first, limit);
58 impl->cbc_wait(priv);
64 const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); local
67 impl->zbc_clear_color(priv, index, color);
74 const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); local
77 impl->zbc_clear_depth(priv, index, depth);
84 const struct nvkm_ltc_impl *impl = (void *)nv_oclass(object); local
93 impl->zbc_clear_color(priv, i, priv->zbc_color[i]);
94 impl
104 const struct nvkm_ltc_impl *impl = (void *)oclass; local
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/drivers/gpu/drm/nouveau/core/subdev/gpio/
H A Dbase.c34 const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; local
35 return impl->drive ? impl->drive(gpio, line, dir, out) : -ENODEV;
41 const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; local
42 return impl->sense ? impl->sense(gpio, line) : -ENODEV;
112 const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; local
113 impl->intr_mask(gpio, type, 1 << index, 0);
120 const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; local
121 impl
142 const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; local
166 const struct nouveau_gpio_impl *impl = (void *)object->oclass; local
217 const struct nouveau_gpio_impl *impl = (void *)oclass; local
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/drivers/gpu/drm/nouveau/dispnv04/
H A Ddisp.h132 const int impl = dev->pdev->device & 0x0ff0; local
134 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 &&
135 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
151 const int impl = dev->pdev->device & 0x0ff0; local
153 if (impl == 0x0310 || impl == 0x0340 || drm->device.info.family >= NV_DEVICE_INFO_V0_CURIE)
/drivers/gpu/drm/nouveau/core/subdev/bus/
H A Dnv04.c70 struct nv04_bus_impl *impl = (void *)oclass; local
79 nv_subdev(priv)->intr = impl->intr;
80 priv->base.hwsq_exec = impl->hwsq_exec;
81 priv->base.hwsq_size = impl->hwsq_size;
/drivers/cpufreq/
H A Dsparc-us3-cpufreq.c167 unsigned long manuf, impl, ver; local
175 impl = ((ver >> 32) & 0xffff);
178 (impl == CHEETAH_IMPL ||
179 impl == CHEETAH_PLUS_IMPL ||
180 impl == JAGUAR_IMPL ||
181 impl == PANTHER_IMPL)) {
H A Dsparc-us2e-cpufreq.c312 unsigned long manuf, impl, ver; local
320 impl = ((ver >> 32) & 0xffff);
322 if (manuf == 0x17 && impl == 0x13) {
/drivers/gpu/drm/nouveau/core/engine/graph/
H A Dctxnvd7.c184 const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); local
185 const u32 alpha = impl->alpha_nr;
186 const u32 beta = impl->attrib_nr;
187 const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
194 u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
210 bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc];
212 ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc];
H A Dctxgm107.c864 const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); local
865 const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
866 impl->bundle_size / 0x20);
867 const u32 token_limit = impl->bundle_token_limit;
870 const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
872 mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);
874 mmio_refn(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s), 0, b);
881 const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); local
884 const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
897 const struct nvc0_grctx_oclass *impl local
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H A Dctxnvc1.c733 const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); local
734 const u32 alpha = impl->alpha_nr;
735 const u32 beta = impl->attrib_nr;
736 const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
743 u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
759 bo += impl->attrib_nr_max;
761 ao += impl->alpha_nr_max;
H A Dctxnve4.c844 const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); local
845 const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
846 impl->bundle_size / 0x20);
847 const u32 token_limit = impl->bundle_token_limit;
850 const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
852 mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);
854 mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b);
861 const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); local
864 const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
H A Dctxnvc0.c1026 const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); local
1029 const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
1031 mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);
1033 mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b);
1039 const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); local
1042 const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
1053 const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); local
1054 const u32 attrib = impl->attrib_nr;
1055 const u32 size = 0x20 * (impl->attrib_nr_max + impl
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/drivers/gpu/drm/nouveau/core/engine/dmaobj/
H A Dbase.c39 const struct nvkm_dmaeng_impl *impl = (void *) local
48 ret = impl->bind(dmaobj, parent, pgpuobj);
54 return impl->bind(dmaobj, parent, pgpuobj);
152 const struct nvkm_dmaeng_impl *impl = (void *)oclass; local
162 nv_engine(dmaeng)->sclass = impl->sclass;
/drivers/gpu/drm/nouveau/core/subdev/i2c/
H A Dbase.c334 const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass; local
336 impl->aux_mask(i2c, type, 1 << port->aux, 0);
344 const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass; local
346 impl->aux_mask(i2c, type, 1 << port->aux, 1 << port->aux);
366 struct nouveau_i2c_impl *impl = (void *)nv_oclass(subdev); local
371 if (impl->aux_stat) {
372 impl->aux_stat(i2c, &hi, &lo, &rq, &tx);
405 struct nouveau_i2c_impl *impl = (void *)nv_oclass(object); local
417 if ((mask = (1 << impl->aux) - 1), impl
482 const struct nouveau_i2c_impl *impl = (void *)oclass; local
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/drivers/gpu/drm/nouveau/core/subdev/pwr/
H A Dbase.c32 const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr); local
33 if (impl->pgob)
34 impl->pgob(ppwr, enable);
189 const struct nvkm_pwr_impl *impl = (void *)object->oclass; local
211 for (i = 0; i < impl->data.size / 4; i++)
212 nv_wr32(ppwr, 0x10a1c4, impl->data.data[i]);
216 for (i = 0; i < impl->code.size / 4; i++) {
219 nv_wr32(ppwr, 0x10a184, impl->code.data[i]);
/drivers/gpu/drm/nouveau/core/subdev/mc/
H A Dbase.c31 const struct nouveau_mc_oclass *impl = (void *)nv_oclass(pmc); local
32 if (impl->unk260)
33 impl->unk260(pmc, data);
/drivers/gpu/drm/nouveau/core/subdev/instmem/
H A Dbase.c76 struct nouveau_instmem_impl *impl = (void *)engine->oclass; local
78 return nouveau_object_ctor(parent, engine, impl->instobj, &args,
/drivers/gpu/drm/nouveau/core/engine/disp/
H A Ddport.c55 struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); local
88 ret = impl->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000,
97 impl->lnk_pwr(outp, dp->link_nr);
111 struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); local
116 impl->pattern(outp, pattern);
127 struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); local
154 impl->drv_ctl(outp, i, lvsw & 3, lpre & 3, lpc2 & 3);
H A Dbase.c191 struct nouveau_disp_impl *impl = (void *)oclass; local
219 sclass = impl->outp;
237 ret = nvkm_event_init(impl->vblank, 1, heads, &disp->vblank);
H A Dnv50.c55 const struct nv50_disp_chan_impl *impl = (void *)oclass->ofuncs; local
58 int chid = impl->chid + head;
73 nv_parent(chan)->object_attach = impl->attach;
74 nv_parent(chan)->object_detach = impl->detach;
343 const struct nv50_disp_impl *impl = (void *)disp->oclass; local
370 nv50_disp_mthd_list(priv, debug, base, impl->mthd.prev,
980 const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine); local
1030 return impl->head.scanoutpos(object, priv, data, size, head);
1325 struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; local
1350 impl
1876 struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; local
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H A Dnvd0.c1089 struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; local
1100 nv50_disp_mthd_chan(priv, NV_DBG_DEBUG, 0, impl->mthd.core);
1145 const struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; local
1158 impl->mthd.core);
1168 impl->mthd.base);
1178 impl->mthd.ovly);
/drivers/gpu/drm/nouveau/core/engine/fifo/
H A Dnve0.c1054 struct nve0_fifo_impl *impl = (void *)oclass; local
1059 impl->channels - 1, &priv);
1080 ret = nouveau_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200,

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