/drivers/video/fbdev/omap2/dss/ |
H A D | dispc-compat.h | 24 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
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H A D | dispc-compat.c | 642 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, argument 650 irqmask); 658 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
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/drivers/gpu/drm/msm/mdp/ |
H A D | mdp_kms.c | 35 uint32_t irqmask = mdp_kms->vblank_mask; local 40 irqmask |= irq->irqmask; 42 mdp_kms->funcs->set_irqmask(mdp_kms, irqmask); 61 if (handler->irqmask & status) { 63 handler->irq(handler, handler->irqmask & status); 94 void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask) argument 99 .irqmask = irqmask,
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H A D | mdp_kms.h | 33 void (*set_irqmask)(struct mdp_kms *mdp_kms, uint32_t irqmask); 68 uint32_t irqmask; member in struct:mdp_irq 75 void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask);
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/drivers/gpu/drm/omapdrm/ |
H A D | omap_irq.c | 35 uint32_t irqmask = priv->vblank_mask; local 40 irqmask |= irq->irqmask; 42 DBG("irqmask=%08x", irqmask); 44 dispc_write_irqenable(irqmask); 113 uint32_t irqmask, int count) 117 wait->irq.irqmask = irqmask; 214 if (handler->irqmask 112 omap_irq_wait_init(struct drm_device *dev, uint32_t irqmask, int count) argument [all...] |
H A D | omap_drv.h | 76 uint32_t irqmask; member in struct:omap_drm_irq 85 uint32_t irqmask, int count);
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H A D | omap_crtc.c | 707 omap_crtc->apply_irq.irqmask = pipe2vbl(crtc); 710 omap_crtc->error_irq.irqmask =
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H A D | omap_plane.c | 417 omap_plane->error_irq.irqmask = error_irqs[id];
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/drivers/gpu/drm/msm/mdp/mdp4/ |
H A D | mdp4_irq.c | 22 void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask) argument 24 mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask); local 45 error_handler->irqmask = MDP4_IRQ_PRIMARY_INTF_UDERRUN |
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H A D | mdp4_kms.h | 177 void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask);
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H A D | mdp4_crtc.c | 661 return mdp4_crtc->vblank.irqmask; 776 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma); 779 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
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/drivers/gpu/drm/msm/mdp/mdp5/ |
H A D | mdp5_irq.c | 22 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask) argument 24 mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask); local 45 error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN |
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H A D | mdp5_crtc.c | 438 return mdp5_crtc->vblank.irqmask; 459 mdp5_crtc->err.irqmask = intf2err(intf); 460 mdp5_crtc->vblank.irqmask = intf2vblank(intf);
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H A D | mdp5_kms.h | 193 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask);
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/drivers/regulator/ |
H A D | lp8755.c | 50 unsigned int irqmask; member in struct:lp8755_chip 374 && (pchip->irqmask & (0x04 << icnt)) 390 if ((flag1 & 0x01) && (pchip->irqmask & 0x01)) 398 if ((flag1 & 0x02) && (pchip->irqmask & 0x02)) 424 pchip->irqmask = regval;
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/drivers/ata/ |
H A D | pata_hpt3x2n.c | 494 u8 irqmask; local 543 pci_read_config_byte(dev, 0x5A, &irqmask); 544 irqmask &= ~0x10; 545 pci_write_config_byte(dev, 0x5a, irqmask);
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H A D | pata_hpt37x.c | 826 u8 irqmask; local 918 pci_read_config_byte(dev, 0x5A, &irqmask); 919 irqmask &= ~0x10; 920 pci_write_config_byte(dev, 0x5a, irqmask);
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H A D | pata_icside.c | 66 unsigned int irqmask; member in struct:pata_icside_info 383 info->irqmask = 1; 444 ec->irqmask = info->irqmask;
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/drivers/media/rc/ |
H A D | winbond-cir.c | 212 u8 irqmask; member in struct:wbcir_data 277 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) argument 279 if (data->irqmask == irqmask) 283 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); 284 data->irqmask = irqmask; 493 status &= data->irqmask;
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/drivers/scsi/arm/ |
H A D | arxescsi.c | 297 ec->irqmask = CSTATUS_IRQ;
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H A D | cumana_2.c | 425 ec->irqmask = STATUS_INT;
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/drivers/net/ethernet/nvidia/ |
H A D | forcedeth.c | 780 u32 irqmask; member in struct:fe_priv 1099 /* In MSIX mode, a write to irqmask behaves as XOR */ 3572 if (np->irqmask != NVREG_IRQMASK_CPU) { 3573 np->irqmask = NVREG_IRQMASK_CPU; 3582 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { 3583 np->irqmask = NVREG_IRQMASK_THROUGHPUT; 3605 if (!(np->events & np->irqmask)) 3638 if (!(np->events & np->irqmask)) 3667 if (!(events & np->irqmask)) 3747 np->nic_poll_irq = np->irqmask; 3905 set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) argument [all...] |
/drivers/media/pci/ivtv/ |
H A D | ivtv-driver.c | 315 itv->irqmask &= ~mask; 316 write_reg_sync(itv->irqmask, IVTV_REG_IRQMASK); 321 itv->irqmask |= mask; 322 write_reg_sync(itv->irqmask, IVTV_REG_IRQMASK);
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H A D | ivtv-irq.c | 938 combo = ~itv->irqmask & stat; 947 if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) { 1013 if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) {
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/drivers/mmc/host/ |
H A D | mmci.c | 783 unsigned int datactrl, timeout, irqmask; local 853 irqmask = MCI_RXFIFOHALFFULLMASK; 861 irqmask |= MCI_RXDATAAVLBLMASK; 867 irqmask = MCI_TXFIFOHALFEMPTYMASK; 872 mmci_set_mask1(host, irqmask);
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