Searched refs:link_nr (Results 1 - 14 of 14) sorted by relevance

/drivers/gpu/drm/nouveau/
H A Dnouveau_dp.c71 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
74 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
76 nv_encoder->dcb->dpconf.link_nr,
79 if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
80 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
85 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
H A Dnouveau_encoder.h59 int link_nr; member in struct:nouveau_encoder::__anon907::__anon908
H A Dnouveau_bios.c1486 entry->dpconf.link_nr = 4;
1489 entry->dpconf.link_nr = 2;
1492 entry->dpconf.link_nr = 1;
H A Dnouveau_connector.c845 max_clock = nv_encoder->dp.link_nr;
/drivers/gpu/drm/nouveau/core/engine/disp/
H A Ddport.c43 int link_nr; member in struct:dp_state
71 DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
88 ret = impl->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000,
97 impl->lnk_pwr(outp, dp->link_nr);
101 sink[1] = dp->link_nr;
131 for (i = 0; i < dp->link_nr; i++) {
212 for (i = 0; i < dp->link_nr; i++) {
250 for (i = 0; i < dp->link_nr && eq_done; i++) {
340 if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) {
342 outp->dpcd[2] |= outp->base.info.dpconf.link_nr;
[all...]
H A Doutpdp.c87 outp->base.info.dpconf.link_nr;
H A Dnvd0.c991 u32 datarate, link_nr, link_bw, bits; local
994 link_nr = hweight32(dpctrl & 0x000f0000);
1002 value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
1009 value = value - ((36 / link_nr) + 3) - 1;
1020 do_div(ratio, link_nr * link_bw);
H A Dnv50.c1651 u32 link_nr, link_bw, bits; local
1655 link_nr = hweight32(dpctrl & 0x000f0000);
1661 value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
1668 value = value - ((36 / link_nr) + 3) - 1;
1676 link_data_rate = (pclk * bits / 8) / link_nr;
/drivers/thunderbolt/
H A Deeprom.c211 u8 link_nr:1; member in struct:tb_drom_entry_port
297 port->link_nr = entry->link_nr;
382 sw->ports[1].link_nr = 0;
383 sw->ports[2].link_nr = 1;
387 sw->ports[3].link_nr = 0;
388 sw->ports[4].link_nr = 1;
H A Dtb.h39 u8 link_nr:1; member in struct:tb_port
H A Dtb.c41 if (port->dual_link_port && port->link_nr)
44 * Only scan on the primary port (link_nr == 0).
/drivers/gpu/drm/nouveau/core/include/subdev/bios/
H A Ddcb.h49 int link_nr; member in struct:dcb_output::__anon837::__anon841
/drivers/gpu/drm/nouveau/core/subdev/bios/
H A Ddcb.c162 outp->dpconf.link_nr = 4;
165 outp->dpconf.link_nr = 2;
169 outp->dpconf.link_nr = 1;
/drivers/gpu/drm/nouveau/core/subdev/i2c/
H A Danx9805.c34 anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh) argument
40 DBG("ANX9805 train %d 0x%02x %d\n", link_nr, link_bw, enh);
43 nv_wri2cr(mast, chan->addr, 0xa1, link_nr | (enh ? 0x80 : 0x00));

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