Searched refs:pfb (Results 1 - 25 of 50) sorted by relevance

12

/drivers/gpu/drm/nouveau/core/subdev/fb/
H A Dbase.c63 struct nouveau_fb *pfb = (void *)object; local
66 ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend);
70 return nouveau_subdev_fini(&pfb->base, suspend);
76 struct nouveau_fb *pfb = (void *)object; local
79 ret = nouveau_subdev_init(&pfb->base);
83 ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram));
87 for (i = 0; i < pfb->tile.regions; i++)
88 pfb
96 struct nouveau_fb *pfb = (void *)object; local
127 struct nouveau_fb *pfb; local
[all...]
H A Dramnv40.c38 nv40_ram_calc(struct nouveau_fb *pfb, u32 freq) argument
40 struct nouveau_bios *bios = nouveau_bios(pfb);
41 struct nv40_ram *ram = (void *)pfb->ram;
48 nv_error(pfb, "mclk pll data not found\n");
52 ret = nv04_pll_calc(nv_subdev(pfb), &pll, freq,
71 nv40_ram_prog(struct nouveau_fb *pfb) argument
73 struct nouveau_bios *bios = nouveau_bios(pfb);
74 struct nv40_ram *ram = (void *)pfb->ram;
82 u32 vbl = nv_rd32(pfb, 0x600808 + (i * 0x2000));
85 if (vbl != nv_rd32(pfb,
170 nv40_ram_tidy(struct nouveau_fb *pfb) argument
179 struct nouveau_fb *pfb = nouveau_fb(parent); local
[all...]
H A Dnv20.c30 nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, argument
37 pfb->tile.comp(pfb, i, size, flags, tile);
43 nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, argument
47 u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
48 if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
60 nv20_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) argument
66 nouveau_mm_free(&pfb->tags, &tile->tag);
70 nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) argument
72 nv_wr32(pfb,
[all...]
H A Dnv10.c30 nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, argument
39 nv10_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) argument
48 nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) argument
50 nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
51 nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
52 nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
53 nv_rd32(pfb, 0x100240 + (i * 0x10));
H A Dnv41.c30 nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) argument
32 nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
33 nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
34 nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
35 nv_rd32(pfb, 0x100600 + (i * 0x10));
36 nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp);
H A Dnv44.c30 nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, argument
40 nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) argument
42 nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
43 nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
44 nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
45 nv_rd32(pfb, 0x100600 + (i * 0x10));
H A Dramnv20.c32 struct nouveau_fb *pfb = nouveau_fb(parent); local
34 u32 pbus1218 = nv_rd32(pfb, 0x001218);
48 ram->size = (nv_rd32(pfb, 0x10020c) & 0xff000000);
49 ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
50 ram->tags = nv_rd32(pfb, 0x100320);
H A Dramnv41.c32 struct nouveau_fb *pfb = nouveau_fb(parent); local
34 u32 pfb474 = nv_rd32(pfb, 0x100474);
49 ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
50 ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
51 ram->base.tags = nv_rd32(pfb, 0x100320);
H A Dramnv49.c32 struct nouveau_fb *pfb = nouveau_fb(parent); local
34 u32 pfb914 = nv_rd32(pfb, 0x100914);
49 ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
50 ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
51 ram->base.tags = nv_rd32(pfb, 0x100320);
H A Dramnv10.c32 struct nouveau_fb *pfb = nouveau_fb(parent); local
34 u32 cfg0 = nv_rd32(pfb, 0x100200);
47 ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
H A Dramnv1a.c32 struct nouveau_fb *pfb = nouveau_fb(parent); local
40 nv_fatal(pfb, "no bridge device\n");
49 if (nv_device(pfb)->chipset == 0x1a) {
H A Dpriv.h45 struct nouveau_fb *pfb = (p); \
46 _nouveau_fb_dtor(nv_object(pfb)); \
49 struct nouveau_fb *pfb = (p); \
50 _nouveau_fb_init(nv_object(pfb)); \
53 struct nouveau_fb *pfb = (p); \
54 _nouveau_fb_fini(nv_object(pfb), (s)); \
H A Dramnv4e.c32 struct nouveau_fb *pfb = nouveau_fb(parent); local
41 ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
H A Dramnv50.c66 nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) argument
68 struct nouveau_bios *bios = nouveau_bios(pfb);
69 struct nv50_ram *ram = (void *)pfb->ram;
88 nv_error(pfb, "invalid/missing perftab entry\n");
94 strap = nvbios_ramcfg_index(nv_subdev(pfb));
96 nv_error(pfb, "invalid ramcfg strap\n");
108 nv_error(pfb, "invalid/missing timing entry "
117 ret = ram_init(hwsq, nv_subdev(pfb));
138 ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq,
208 nv50_ram_prog(struct nouveau_fb *pfb) argument
219 nv50_ram_tidy(struct nouveau_fb *pfb) argument
227 __nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem *mem) argument
242 nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) argument
258 nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, u32 memtype, struct nouveau_mem **pmem) argument
320 nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram) argument
362 struct nouveau_fb *pfb = nouveau_fb(parent); local
[all...]
H A Dramnvaa.c34 struct nouveau_fb *pfb = nouveau_fb(parent); local
43 ram->size = nv_rd32(pfb, 0x10020c);
46 ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) -
52 ram->stolen = (u64)nv_rd32(pfb, 0x100e10) << 12;
H A Dramnvc0.c114 struct nouveau_fb *pfb = nouveau_fb(ram); local
115 u32 part = nv_rd32(pfb, 0x022438), i;
116 u32 mask = nv_rd32(pfb, 0x022554);
130 nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) argument
132 struct nouveau_clock *clk = nouveau_clock(pfb);
133 struct nouveau_bios *bios = nouveau_bios(pfb);
134 struct nvc0_ram *ram = (void *)pfb->ram;
151 nv_error(pfb, "invalid/missing rammap entry\n");
156 strap = nvbios_ramcfg_index(nv_subdev(pfb));
158 nv_error(pfb, "invali
407 nvc0_ram_prog(struct nouveau_fb *pfb) argument
417 nvc0_ram_tidy(struct nouveau_fb *pfb) argument
427 nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) argument
446 nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, u32 memtype, struct nouveau_mem **pmem) argument
512 struct nouveau_fb *pfb = nouveau_fb(parent); local
582 struct nouveau_fb *pfb = (void *)object->parent; local
[all...]
H A Dramgk20a.c35 gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) argument
37 struct device *dev = nv_device_base(nv_device(pfb));
53 gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, argument
56 struct device *dev = nv_device_base(nv_device(pfb));
62 nv_debug(pfb, "%s: size: %llx align: %x, ncmin: %x\n", __func__, size,
100 nv_error(pfb, "%s: cannot allocate memory!\n", __func__);
101 gk20a_ram_put(pfb, pmem);
109 nv_warn(pfb, "memory not aligned as requested: %pad (0x%x)\n",
112 nv_debug(pfb, "alloc size: 0x%x, align: 0x%x, paddr: %pad, vaddr: %p\n",
H A Dnv25.c30 nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, argument
34 u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
35 if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
H A Dnv35.c30 nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, argument
34 u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
35 if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
H A Dnv36.c30 nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, argument
34 u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
35 if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
H A Dnv40.c30 nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, argument
34 u32 tags = round_up(tiles / pfb->ram->parts, 0x100);
36 !nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
H A Dramnv44.c32 struct nouveau_fb *pfb = nouveau_fb(parent); local
34 u32 pfb474 = nv_rd32(pfb, 0x100474);
49 ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
H A Dnv30.c30 nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, argument
37 if (pfb->tile.comp) /* z compression */
38 pfb->tile.comp(pfb, i, size, flags, tile);
49 nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, argument
53 u32 tags = round_up(tiles / pfb->ram->parts, 0x40);
54 if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
H A Dramnva3.c76 nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) argument
78 struct nouveau_bios *bios = nouveau_bios(pfb);
79 struct nva3_ram *ram = (void *)pfb->ram;
103 nv_error(pfb, "invalid/missing rammap entry\n");
108 strap = nvbios_ramcfg_index(nv_subdev(pfb));
110 nv_error(pfb, "invalid ramcfg strap\n");
117 nv_error(pfb, "invalid/missing ramcfg entry\n");
127 nv_error(pfb, "invalid/missing timing entry\n");
132 ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
134 nv_error(pfb, "faile
311 nva3_ram_prog(struct nouveau_fb *pfb) argument
321 nva3_ram_tidy(struct nouveau_fb *pfb) argument
331 struct nouveau_fb *pfb = (void *)object->parent; local
[all...]
/drivers/gpu/drm/gma500/
H A Dframebuffer.h39 struct psb_framebuffer pfb; member in struct:psb_fbdev

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