Searched refs:pll_clk (Results 1 - 8 of 8) sorted by relevance
| /drivers/clk/socfpga/ |
| H A D | clk-pll.c | 89 struct socfpga_pll *pll_clk; local
99 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
100 if (WARN_ON(!pll_clk))
106 pll_clk->hw.reg = clk_mgr_base_addr + reg;
120 pll_clk->hw.hw.init = &init;
122 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
126 clk = clk_register(NULL, &pll_clk->hw.hw);
128 kfree(pll_clk);
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| /drivers/clk/ |
| H A D | clk-moxart.c | 59 struct clk *clk, *pll_clk; local
81 pll_clk = of_clk_get(node, 0);
82 if (IS_ERR(pll_clk)) {
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| H A D | clk-vt8500.c | 654 struct clk_pll *pll_clk; local
667 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
668 if (WARN_ON(!pll_clk))
671 pll_clk->reg = pmc_base + reg;
672 pll_clk->lock = &_lock;
673 pll_clk->type = pll_type;
684 pll_clk->hw.init = &init;
686 clk = clk_register(NULL, &pll_clk->hw);
688 kfree(pll_clk);
[all...] |
| /drivers/clk/rockchip/ |
| H A D | clk-pll.c | 291 struct clk *pll_clk, *mux_clk; local
350 pll_clk = clk_register(NULL, &pll->hw);
351 if (IS_ERR(pll_clk)) {
353 __func__, name, PTR_ERR(pll_clk));
354 mux_clk = pll_clk;
390 clk_unregister(pll_clk);
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| /drivers/clk/samsung/ |
| H A D | clk-pll.c | 1148 struct samsung_pll_clock *pll_clk,
1159 __func__, pll_clk->name);
1163 init.name = pll_clk->name;
1164 init.flags = pll_clk->flags;
1165 init.parent_names = &pll_clk->parent_name;
1168 if (pll_clk->rate_table) {
1170 for (len = 0; pll_clk->rate_table[len].rate != 0; )
1174 pll->rate_table = kmemdup(pll_clk->rate_table,
1180 __func__, pll_clk->name);
1183 switch (pll_clk
1147 _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) argument
[all...] |
| /drivers/clk/spear/ |
| H A D | clk-vco-pll.c | 279 spinlock_t *lock, struct clk **pll_clk,
350 if (pll_clk)
351 *pll_clk = tpll_clk;
275 clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock, struct clk **pll_clk, struct clk **vco_gate_clk) argument
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| H A D | clk.h | 127 spinlock_t *lock, struct clk **pll_clk,
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| /drivers/gpu/drm/exynos/ |
| H A D | exynos_drm_dsi.c | 280 struct clk *pll_clk; member in struct:exynos_dsi
422 clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate);
424 fin = clk_get_rate(dsi->pll_clk);
1302 ret = clk_prepare_enable(dsi->pll_clk);
1317 clk_disable_unprepare(dsi->pll_clk);
1344 clk_disable_unprepare(dsi->pll_clk);
1718 dsi->pll_clk = devm_clk_get(&pdev->dev, "pll_clk");
1719 if (IS_ERR(dsi->pll_clk)) {
1721 ret = PTR_ERR(dsi->pll_clk);
[all...] |
Completed in 1233 milliseconds