Searched refs:read_reg (Results 1 - 25 of 100) sorted by relevance

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/drivers/edac/
H A Daltera_edac.c149 u32 reg, read_reg; local
159 regmap_read(drvdata->mc_vbase, CTLCFG_OFST, &read_reg);
160 read_reg &= ~(CTLCFG_GEN_SB_ERR | CTLCFG_GEN_DB_ERR);
170 (read_reg | CTLCFG_GEN_DB_ERR));
175 (read_reg | CTLCFG_GEN_SB_ERR));
182 regmap_write(drvdata->mc_vbase, CTLCFG_OFST, read_reg);
193 read_reg = ACCESS_ONCE(ptemp[1]);
198 reg, read_reg);
225 u32 size, read_reg, row, bank, col, cs, width; local
227 if (regmap_read(mc_vbase, DRAMADDRW_OFST, &read_reg) <
261 u32 read_reg, mem_size; local
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/drivers/media/radio/
H A Dradio-tea5777.h61 int (*read_reg)(struct radio_tea5777 *tea, u32 *val); member in struct:radio_tea5777_ops
76 u32 read_reg; member in struct:radio_tea5777
H A Dradio-tea5777.c232 tea->read_reg = -1;
242 if (tea->read_reg != -1)
256 res = tea->ops->read_reg(tea, &tea->read_reg);
323 (tea->read_reg & TEA5777_R_FM_STEREO_MASK))
329 v->signal = (tea->read_reg & TEA5777_R_LEVEL_MASK) >>
332 /* Invalidate read_reg, so that next call we return up2date signal */
333 tea->read_reg = -1;
476 tea->freq = (tea->read_reg & TEA5777_R_FM_PLL_MASK);
479 if ((tea->read_reg
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/drivers/media/pci/ivtv/
H A Divtv-gpio.c113 curout = read_reg(IVTV_REG_GPIO_OUT);
114 curdir = read_reg(IVTV_REG_GPIO_DIR);
137 curout = read_reg(IVTV_REG_GPIO_OUT);
177 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT);
187 if (mask == 0 || (read_reg(IVTV_REG_GPIO_IN) & mask))
218 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT);
230 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT);
256 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT);
271 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) |
284 read_reg(IVTV_REG_GPIO_DI
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H A Divtv-yuv.c864 yi->reg_2834 = read_reg(0x02834);
865 yi->reg_2838 = read_reg(0x02838);
866 yi->reg_283c = read_reg(0x0283c);
867 yi->reg_2840 = read_reg(0x02840);
868 yi->reg_2844 = read_reg(0x02844);
869 yi->reg_2848 = read_reg(0x02848);
870 yi->reg_2854 = read_reg(0x02854);
871 yi->reg_285c = read_reg(0x0285c);
872 yi->reg_2864 = read_reg(0x02864);
873 yi->reg_2870 = read_reg(
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/drivers/net/can/sja1000/
H A Dsja1000.c95 priv->read_reg(priv, SJA1000_SR);
101 return (priv->read_reg(priv, SJA1000_MOD) == 0xFF);
118 unsigned char status = priv->read_reg(priv, SJA1000_MOD);
134 status = priv->read_reg(priv, SJA1000_MOD);
143 unsigned char status = priv->read_reg(priv, SJA1000_MOD);
169 status = priv->read_reg(priv, SJA1000_MOD);
213 if (!(priv->read_reg(priv, SJA1000_CDR) & CDR_PELICAN))
219 priv->read_reg(priv, SJA1000_ECC);
266 bec->txerr = priv->read_reg(priv, SJA1000_TXERR);
267 bec->rxerr = priv->read_reg(pri
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H A Dsja1000_platform.c84 priv->read_reg = sp_read_reg32;
88 priv->read_reg = sp_read_reg16;
93 priv->read_reg = sp_read_reg8;
110 priv->read_reg = sp_read_reg32;
114 priv->read_reg = sp_read_reg16;
119 priv->read_reg = sp_read_reg8;
H A Dplx_pci.c369 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
371 (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) &&
372 (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL))
382 if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL &&
383 priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL &&
384 priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL)
580 priv->read_reg = plx_pci_read_reg;
/drivers/media/usb/dvb-usb-v2/
H A Dmxl111sf-demod.h29 int (*read_reg)(struct mxl111sf_state *state, u8 addr, u8 *data); member in struct:mxl111sf_demod_config
H A Dmxl111sf-tuner.h53 int (*read_reg)(struct mxl111sf_state *state, u8 addr, u8 *data); member in struct:mxl111sf_tuner_config
/drivers/macintosh/
H A Dtherm_windtunnel.c138 read_reg( struct i2c_client *cl, int reg, int len ) function
173 temp = read_reg( x.thermostat, 0, 2 );
179 casetemp = read_reg(x.fan, 0x0b, 1) << 8;
180 casetemp |= (read_reg(x.fan, 0x06, 1) & 0x7) << 5;
215 x.r0 = read_reg( x.fan, 0x00, 1 );
216 x.r1 = read_reg( x.fan, 0x01, 1 );
217 x.r20 = read_reg( x.fan, 0x20, 1 );
218 x.r23 = read_reg( x.fan, 0x23, 1 );
219 x.r25 = read_reg( x.fan, 0x25, 1 );
222 if( (val=read_reg(
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H A Dtherm_adt746x.c110 read_reg(struct thermostat* th, int reg) function
133 tmp[1] = read_reg(th, addr);
134 tmp[0] = read_reg(th, addr + 1);
173 manual = read_reg(th, MANUAL_MODE[fan]);
181 manual = read_reg(th,
188 manual = read_reg(th, MANUAL_MODE[fan]);
203 th->temps[i] = read_reg(th, TEMP_REG[i]);
374 BUILD_SHOW_FUNC_INT(sensor1_temperature, (read_reg(th, TEMP_REG[1])))
375 BUILD_SHOW_FUNC_INT(sensor2_temperature, (read_reg(th, TEMP_REG[2])))
507 rc = read_reg(t
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/drivers/net/ethernet/intel/igb/
H A De1000_phy.c86 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
92 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
497 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
511 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
556 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
605 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
658 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
785 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
815 ret_val = phy->ops.read_reg(hw,
829 ret_val = phy->ops.read_reg(h
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/drivers/net/can/
H A Dxilinx_can.c124 * @read_reg: For reading data from CAN registers
138 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg); member in struct:xcan_priv
232 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) {
260 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) &
284 priv->read_reg(priv, XCAN_BRPR_OFFSET),
285 priv->read_reg(priv, XCAN_BTR_OFFSET));
332 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) {
340 priv->read_reg(priv, XCAN_SR_OFFSET));
399 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) &
488 id_xcan = priv->read_reg(pri
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/drivers/gpio/
H A Dgpio-it8761e.c47 static u8 read_reg(u8 addr, u8 port) function
102 curr_dirs = read_reg(io_reg, port);
148 curr_dirs = read_reg(io_reg, port);
177 id = (read_reg(CHIP_ID_HIGH_BYTE, ports[i]) << 8) +
178 read_reg(CHIP_ID_LOW_BYTE, ports[i]);
195 gpio_ba = (read_reg(GPIO_BA_HIGH_BYTE, port) << 8) +
196 read_reg(GPIO_BA_LOW_BYTE, port);
H A Dgpio-generic.c142 return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
278 bgc->read_reg = bgpio_read8;
283 bgc->read_reg = bgpio_read16be;
286 bgc->read_reg = bgpio_read16;
292 bgc->read_reg = bgpio_read32be;
295 bgc->read_reg = bgpio_read32;
306 bgc->read_reg = bgpio_read64;
440 bgc->data = bgc->read_reg(bgc->reg_dat);
443 bgc->data = bgc->read_reg(bgc->reg_set);
445 bgc->dir = bgc->read_reg(bg
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/drivers/block/paride/
H A Dpt.c256 static inline int read_reg(struct pi_adapter *pi, int reg) function
282 s = read_reg(pi, 7);
283 e = read_reg(pi, 1);
284 p = read_reg(pi, 2);
317 if (read_reg(pi, 2) != 1) {
336 if (read_reg(pi, 7) & STAT_DRQ) {
337 n = (((read_reg(pi, 4) + 256 * read_reg(pi, 5)) +
339 p = read_reg(pi, 2) & 3;
406 s = read_reg(p
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H A Dpg.c267 static inline int read_reg(struct pg *dev, int reg) function
305 s = read_reg(dev, 7);
306 e = read_reg(dev, 1);
307 p = read_reg(dev, 2);
337 if (read_reg(dev, 2) != 1) {
365 while (read_reg(dev, 7) & STAT_DRQ) {
366 d = (read_reg(dev, 4) + 256 * read_reg(dev, 5));
368 p = read_reg(dev, 2) & 3;
404 got[i] = read_reg(de
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/drivers/net/can/c_can/
H A Dc_can_pci.c90 val = priv->read_reg(priv, index);
91 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
192 priv->read_reg = c_can_pci_read_reg_aligned_to_32bit;
196 priv->read_reg = c_can_pci_read_reg_aligned_to_16bit;
200 priv->read_reg = c_can_pci_read_reg_32bit;
H A Dc_can.c242 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK;
258 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY))
405 data = priv->read_reg(priv, dreg);
474 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
508 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
643 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
670 clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG);
749 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX));
781 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG);
875 reg_err_counter = priv->read_reg(pri
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H A Dc_can_platform.c116 val = priv->read_reg(priv, index);
117 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
244 priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
251 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
261 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
/drivers/ide/
H A Dopti621.c52 static u8 read_reg(int reg) function
102 read_reg(CNTRL_REG);
105 clk = read_reg(STRAP_REG) & 1;
/drivers/media/i2c/
H A Dtw2804.c137 static int read_reg(struct i2c_client *client, u8 reg, u8 channel) function
183 ctrl->val = read_reg(client, TW2804_REG_GAIN, 0);
187 ctrl->val = read_reg(client, TW2804_REG_CHROMA_GAIN, 0);
191 ctrl->val = read_reg(client, TW2804_REG_BLUE_BALANCE, 0);
195 ctrl->val = read_reg(client, TW2804_REG_RED_BALANCE, 0);
211 reg = read_reg(client, addr, state->channel);
222 reg = read_reg(client, addr, state->channel);
322 reg = read_reg(client, 0x22, dec->channel);
/drivers/mtd/onenand/
H A Domap2.c82 static inline unsigned short read_reg(struct omap2_onenand *c, int reg) function
134 intr = read_reg(c, ONENAND_REG_INTERRUPT);
138 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
152 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
158 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
165 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
166 intr = read_reg(c, ONENAND_REG_INTERRUPT);
179 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
189 intr = read_reg(c,
194 intr = read_reg(
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/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_phy.c72 hw->phy.ops.read_reg(hw,
133 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
138 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
216 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
456 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
471 hw->phy.ops.read_reg(hw,
488 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
507 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
567 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
610 status = hw->phy.ops.read_reg(h
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