Searched refs:ref_clk (Results 1 - 20 of 20) sorted by relevance

/drivers/clk/
H A Dclk-moxart.c21 struct clk *clk, *ref_clk; local
38 ref_clk = of_clk_get(node, 0);
39 if (IS_ERR(ref_clk)) {
/drivers/phy/
H A Dphy-samsung-usb2.h39 struct clk *ref_clk; member in struct:samsung_usb2_phy_driver
H A Dphy-samsung-usb2.c33 ret = clk_prepare_enable(drv->ref_clk);
63 clk_disable_unprepare(drv->ref_clk);
187 drv->ref_clk = devm_clk_get(dev, "ref");
188 if (IS_ERR(drv->ref_clk)) {
190 return PTR_ERR(drv->ref_clk);
193 drv->ref_rate = clk_get_rate(drv->ref_clk);
H A Dphy-exynos5-usbdrd.c156 * @ref_clk: reference clock to PHY block from which PHY's
173 struct clk *ref_clk; member in struct:exynos5_usbdrd_phy
449 clk_prepare_enable(phy_drd->ref_clk);
466 clk_disable_unprepare(phy_drd->ref_clk);
485 clk_disable_unprepare(phy_drd->ref_clk);
585 phy_drd->ref_clk = devm_clk_get(dev, "ref");
586 if (IS_ERR(phy_drd->ref_clk)) {
588 return PTR_ERR(phy_drd->ref_clk);
590 ref_rate = clk_get_rate(phy_drd->ref_clk);
/drivers/spi/
H A Dspi-cadence.c104 * @ref_clk: Pointer to the peripheral clock
116 struct clk *ref_clk; member in struct:cdns_spi
255 frequency = clk_get_rate(xspi->ref_clk);
500 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
501 if (IS_ERR(xspi->ref_clk)) {
502 dev_err(&pdev->dev, "ref_clk clock not found.\n");
503 ret = PTR_ERR(xspi->ref_clk);
513 ret = clk_prepare_enable(xspi->ref_clk);
558 master->max_speed_hz = clk_get_rate(xspi->ref_clk) /
[all...]
/drivers/gpu/drm/i915/
H A Dintel_dsi_pll.c168 u32 ref_clk; local
183 ref_clk = 25000;
194 calc_dsi_clk = (m * ref_clk) / p;
/drivers/gpu/drm/radeon/
H A Drv6xx_dpm.c164 u32 ref_clk = rdev->clock.spll.reference_freq; local
184 fb_divider = ((step->vco_frequency * pi->spll_ref_div) / ref_clk) >>
429 u32 ref_clk = rdev->clock.spll.reference_freq; local
431 return rv6xx_scale_count_given_unit(rdev, delay_us * (ref_clk / 100), unit);
552 u32 ref_clk = rdev->clock.spll.reference_freq; local
562 vco_freq = rv6xx_calculate_vco_frequency(ref_clk, &dividers,
568 (ref_clk / (dividers.ref_div + 1)),
574 (ref_clk / (dividers.ref_div + 1)));
633 u32 ref_clk,
643 vco_freq_temp = rv6xx_calculate_vco_frequency(ref_clk,
631 rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev, u32 requested_memory_clock, u32 ref_clk, struct atom_clock_dividers *dividers, u32 *vco_freq) argument
656 u32 ref_clk = rdev->clock.mpll.reference_freq; local
841 u32 ref_clk = rdev->clock.spll.reference_freq; local
[all...]
H A Dcypress_dpm.c443 u32 ref_clk = rdev->clock.mpll.reference_freq; local
444 u32 vco = clkf * ref_clk;
447 if (ref_clk == 10000) {
/drivers/net/wireless/cw1200/
H A Dcw1200_sdio.c34 .ref_clk = 38400,
309 self->pdata->ref_clk,
H A Dcw1200.h297 int ref_clk, const u8 *macaddr,
H A Dmain.c518 int ref_clk, const u8 *macaddr,
534 priv->hw_refclk = ref_clk;
514 cw1200_core_probe(const struct hwbus_ops *hwbus_ops, struct hwbus_priv *hwbus, struct device *pdev, struct cw1200_common **core, int ref_clk, const u8 *macaddr, const char *sdd_path, bool have_5ghz) argument
H A Dcw1200_spi.c419 self->pdata->ref_clk,
/drivers/video/fbdev/aty/
H A Dradeon_base.c439 rinfo->pll.ref_clk = (*val) / 10;
583 rinfo->pll.ref_clk = xtal;
608 rinfo->pll.ref_clk = 2700;
619 rinfo->pll.ref_clk = 2700;
629 rinfo->pll.ref_clk = 2700;
639 rinfo->pll.ref_clk = 2700;
650 rinfo->pll.ref_clk = 2700;
675 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
710 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk
[all...]
H A Datyfb.h51 int ref_clk; member in struct:pll_info
H A Daty128fb.c417 u32 ref_clk; member in struct:aty128_constants
931 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
936 par->constants.ref_clk);
979 if (!par->constants.ref_clk)
980 par->constants.ref_clk = 2950;
988 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
1412 d = c.ref_clk;
H A Dradeonfb.h142 int ref_clk; member in struct:pll_info
H A Datyfb_base.c3422 par->pll_limits.ref_clk = pll_block.ref_freq/100;
/drivers/video/fbdev/mbx/
H A Dmbxfb.c129 unsigned int ref_clk = 13000; /* FIXME: take from platform data */ local
135 /* PLL output freq = (ref_clk * M) / (N * 2^P)
149 clk = (ref_clk * m) / (n * (1 << p));
/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c45 int min_vco, max_vco, p_transition_clk, ref_clk; member in struct:pll_min_max
661 return plls[index].ref_clk * m / n / p;
672 vco = pll->ref_clk * m / n;
974 m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
/drivers/video/fbdev/
H A Dsmscufx.c534 const u32 ref_clk = 25000000; local
539 u32 ref_freq0 = ref_clk / div_r0;

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