/drivers/gpu/drm/tegra/ |
H A D | mipi-phy.c | 19 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, argument 22 timing->clkmiss = 0; 23 timing->clkpost = 70 + 52 * period; 24 timing->clkpre = 8; 25 timing->clkprepare = 65; 26 timing->clksettle = 95; 27 timing->clktermen = 0; 28 timing->clktrail = 80; 29 timing->clkzero = 260; 30 timing 52 mipi_dphy_timing_validate(struct mipi_dphy_timing *timing, unsigned long period) argument [all...] |
H A D | mipi-phy.h | 13 * D-PHY timing parameters 46 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, 48 int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
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/drivers/gpu/drm/nouveau/core/subdev/bios/ |
H A D | timing.c | 28 #include <subdev/bios/timing.h> 35 u16 timing = 0x0000; local 39 timing = nv_ro16(bios, bit_P.offset + 4); 42 timing = nv_ro16(bios, bit_P.offset + 8); 44 if (timing) { 45 *ver = nv_ro08(bios, timing + 0); 48 *hdr = nv_ro08(bios, timing + 1); 49 *cnt = nv_ro08(bios, timing + 2); 50 *len = nv_ro08(bios, timing + 3); 53 return timing; 75 u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); local [all...] |
/drivers/ide/ |
H A D | triflex.c | 41 u16 timing = 0; local 48 timing = 0x0103; 51 timing = 0x0203; 54 timing = 0x0808; 59 timing = 0x0f0f; 62 timing = 0x0202; 65 timing = 0x0204; 68 timing = 0x0404; 71 timing = 0x0508; 74 timing [all...] |
H A D | amd74xx.c | 47 * amd_set_speed() writes timing values to the chipset registers 51 struct ide_timing *timing) 56 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); 60 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); 63 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); 66 case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; 67 case ATA_UDMA4: t = timing 50 amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask, struct ide_timing *timing) argument [all...] |
H A D | ht6560b.c | 76 * Perhaps I should explain something about these timing values: 91 * You can obtain optimized timing values by running Holtek IDESETUP.COM 92 * for DOS. DOS drivers get their timing values from command line, where 120 u8 select, timing; local 125 timing = HT_TIMING(drive); 135 if (select != current_select || timing != current_timing) { 137 current_timing = timing; 144 * Set timing for this drive: 146 outb(timing, hwif->io_ports.device_addr); 149 printk("ht6560b: %s: select=%#x timing 285 u8 timing; local [all...] |
H A D | via82cxxx.c | 117 * via_set_speed - write timing registers 120 * @timing: IDE timing data to use 122 * via_set_speed writes timing values to the chipset registers 125 static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) argument 134 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); 139 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); 142 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing [all...] |
/drivers/video/fbdev/ |
H A D | gbefb.c | 40 struct gbe_timing_info timing; member in struct:gbefb_par 419 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) argument 425 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); 427 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); 435 timing->pll_m = 4; 436 timing->pll_n = 1; 437 timing->pll_p = 0; 464 struct gbe_timing_info *timing) 475 /* Determine valid resolution and timing 511 /* set video timing informatio 463 compute_gbe_timing(struct fb_var_screeninfo *var, struct gbe_timing_info *timing) argument 539 gbe_set_timing_info(struct gbe_timing_info *timing) argument 911 struct gbe_timing_info timing; local [all...] |
/drivers/video/fbdev/via/ |
H A D | via_modesetting.c | 33 void via_set_primary_timing(const struct via_display_timing *timing) argument 37 raw.hor_total = timing->hor_total / 8 - 5; 38 raw.hor_addr = timing->hor_addr / 8 - 1; 39 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; 40 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; 41 raw.hor_sync_start = timing->hor_sync_start / 8; 42 raw.hor_sync_end = timing->hor_sync_end / 8; 43 raw.ver_total = timing->ver_total - 2; 44 raw.ver_addr = timing->ver_addr - 1; 45 raw.ver_blank_start = timing 91 via_set_secondary_timing(const struct via_display_timing *timing) argument [all...] |
H A D | via_modesetting.h | 52 void via_set_primary_timing(const struct via_display_timing *timing); 53 void via_set_secondary_timing(const struct via_display_timing *timing);
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/drivers/ata/ |
H A D | pata_triflex.c | 74 * triflex_load_timing - timing configuration 88 u32 timing = 0; local 100 timing = 0x0103;break; 102 timing = 0x0203;break; 104 timing = 0x0808;break; 108 timing = 0x0F0F;break; 110 timing = 0x0202;break; 112 timing = 0x0204;break; 114 timing = 0x0404;break; 116 timing [all...] |
H A D | pata_cmd640.c | 53 struct cmd640_reg *timing = ap->private_data; local 67 /* The second channel has shared timings and the setup timing is 99 /* Load setup timing */ 115 timing->reg58[adev->devno] = (t.active << 4) | t.recover; 133 struct cmd640_reg *timing = ap->private_data; local 135 if (ap->port_no != 0 && adev->devno != timing->last) { 136 pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]); 137 timing->last = adev->devno; 153 struct cmd640_reg *timing; local 155 timing [all...] |
H A D | pata_cs5530.c | 68 /* Now load the right timing register */ 76 * cs5530_set_dmamode - DMA timing setup 88 u32 tuning, timing = 0; local 96 timing = 0x00921250;break; 98 timing = 0x00911140;break; 100 timing = 0x00911030;break; 102 timing = 0x00077771;break; 104 timing = 0x00012121;break; 106 timing = 0x00002020;break; 111 timing | [all...] |
H A D | pata_sis.c | 314 t1 &= 0xC0C00FFF; /* Mask out timing */ 341 u16 timing; local 346 pci_read_config_word(pdev, drive_pci, &timing); 349 /* bits 3-0 hold recovery timing bits 8-10 active timing and 351 timing &= ~0x870F; 352 timing |= mwdma_bits[speed]; 356 timing &= ~0x6000; 357 timing |= udma_bits[speed]; 359 pci_write_config_word(pdev, drive_pci, timing); 380 u16 timing; local 419 u8 timing; local 453 u8 timing; local [all...] |
H A D | pata_at32.c | 89 * Setup SMC for the given ATA timing. 96 struct smc_timing timing; local 101 memset(&timing, 0, sizeof(struct smc_timing)); 104 timing.read_cycle = ata->cyc8b; 107 timing.nrd_setup = ata->setup; 108 timing.nrd_pulse = ata->act8b; 109 timing.nrd_recover = ata->rec8b; 111 /* Convert nanosecond timing to clock cycles */ 112 smc_set_timing(smc, &timing); 152 struct ata_timing timing; local [all...] |
H A D | pata_sl82c105.c | 16 * timing parameters. 67 * sl82c105_configure_piomode - set chip PIO timing 72 * Called to do the PIO mode setup. Our timing registers are shared 84 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); local 86 pci_write_config_word(pdev, timing, pio_timing[pio]); 88 pci_read_config_word(pdev, timing, &dummy); 96 * Called to do the PIO mode setup. Our timing registers are shared 97 * but we want to set the PIO timing by default. 121 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); local 124 pci_write_config_word(pdev, timing, dma_timin [all...] |
/drivers/media/i2c/ |
H A D | bt819.c | 73 struct timing { struct 83 static struct timing timing_data[] = { 188 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; local 191 (((timing->vdelay >> 8) & 0x03) << 6) | 192 (((timing->vactive >> 8) & 0x03) << 4) | 193 (((timing->hdelay >> 8) & 0x03) << 2) | 194 ((timing->hactive >> 8) & 0x03); 195 init[0x04 * 2 - 1] = timing->vdelay & 0xff; 196 init[0x05 * 2 - 1] = timing 251 struct timing *timing = NULL; local [all...] |
/drivers/char/ |
H A D | bfin-otp.c | 84 * bfin_otp_init_timing - setup OTP timing parameters 90 u32 tp1, tp2, tp3, timing; local 95 timing = tp1 | tp2 | tp3; 96 if (bfrom_OtpCommand(OTP_INIT, timing)) 99 return timing; 107 static void bfin_otp_deinit_timing(u32 timing) argument 111 bfrom_OtpCommand(OTP_INIT, timing & ~(-1 << 15)); 123 u32 timing, page, base_flags, flags, ret; local 137 timing = bfin_otp_init_timing(); 138 if (timing 180 u32 timing; local [all...] |
/drivers/pcmcia/ |
H A D | sa11xx_base.c | 81 struct soc_pcmcia_timing timing; local 86 soc_common_pcmcia_get_timing(skt, &timing); 88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io); 89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem); 90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr); 144 struct soc_pcmcia_timing timing; local 149 soc_common_pcmcia_get_timing(skt, &timing); 151 p+=sprintf(p, "I/O : %u (%u)\n", timing.io, 154 p+=sprintf(p, "attribute: %u (%u)\n", timing.attr, 157 p+=sprintf(p, "common : %u (%u)\n", timing [all...] |
/drivers/cpufreq/ |
H A D | cris-etraxfs-cpufreq.c | 80 reg_bif_core_rw_sdram_timing timing = local 82 timing.cpd = (freqs->new == 200000 ? 0 : 1); 86 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
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/drivers/gpu/drm/nouveau/core/subdev/fb/ |
H A D | sddr3.c | 77 /* XXX: NV50: Get CWL from the timing register */ 87 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; 88 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; 89 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
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H A D | sddr2.c | 73 CL = (ram->next->bios.timing[1] & 0x0000001f); 74 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
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H A D | ramnv50.c | 29 #include <subdev/bios/timing.h> 76 } ramcfg, timing; local 105 timing.data = nvbios_timingEe(bios, strap, &ver, &hdr, 107 if (!timing.data || ver != 0x10 || hdr < 0x12) { 108 nv_error(pfb, "invalid/missing timing entry " 110 strap, timing.data, ver, hdr); 114 timing.data = 0; 178 ram_mask(hwsq, timing[3], 0x00000000, 0x00000000); /*XXX*/ 179 ram_mask(hwsq, timing[1], 0x00000000, 0x00000000); /*XXX*/ 180 ram_mask(hwsq, timing[ [all...] |
/drivers/iio/humidity/ |
H A D | dht11.c | 46 /* Data transmission timing (nano seconds) */ 70 static unsigned char dht11_decode_byte(int *timing, int threshold) argument 77 if (timing[i] >= threshold) 86 int i, t, timing[DHT11_BITS_PER_READ], threshold, local 111 timing[i] = t / timeres; 114 hum_int = dht11_decode_byte(timing, threshold); 115 hum_dec = dht11_decode_byte(&timing[8], threshold); 116 temp_int = dht11_decode_byte(&timing[16], threshold); 117 temp_dec = dht11_decode_byte(&timing[24], threshold); 118 checksum = dht11_decode_byte(&timing[3 [all...] |
/drivers/gpu/drm/rcar-du/ |
H A D | rcar_du_lvdscon.c | 95 struct display_timing timing; local 97 ret = of_get_display_timing(np, "panel-timing", &timing); 101 videomode_from_timing(&timing, &lvdscon->panel.mode);
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