Searched refs:tmp (Results 1 - 25 of 1689) sorted by relevance

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/drivers/video/fbdev/kyro/
H A DSTG4000Ramdac.c29 u32 tmp = 0; local
35 tmp = STG_READ_REG(SoftwareReset);
37 if (tmp & 0x1) {
39 STG_WRITE_REG(SoftwareReset, tmp);
43 tmp = STG_READ_REG(DACPixelFormat);
53 tmp |= _16BPP;
60 tmp |= _32BPP;
67 STG_WRITE_REG(DACPixelFormat, tmp);
76 tmp = STG_READ_REG(DACPrimSize);
79 tmp |
149 u32 tmp; local
158 u32 tmp; local
[all...]
H A DSTG4000VTG.c19 u32 tmp; local
23 tmp = STG_READ_REG(SoftwareReset);
25 STG_WRITE_REG(SoftwareReset, tmp);
33 tmp = STG_READ_REG(SoftwareReset);
34 tmp |= SET_BIT(8);
35 STG_WRITE_REG(SoftwareReset, tmp);
40 u32 tmp = 0; local
43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2);
45 STG_WRITE_REG(DACSyncCtrl, tmp);
50 u32 tmp local
62 u32 tmp = 0; local
[all...]
H A DSTG4000OverlayDevice.c81 u32 tmp; local
84 tmp = STG_READ_REG(DACOverlayAddr);
87 STG_WRITE_REG(DACOverlayAddr, tmp);
90 tmp = STG_READ_REG(DACOverlayUAddr);
92 STG_WRITE_REG(DACOverlayUAddr, tmp);
95 tmp = STG_READ_REG(DACOverlayVAddr);
97 STG_WRITE_REG(DACOverlayVAddr, tmp);
100 tmp = STG_READ_REG(DACOverlaySize);
103 STG_WRITE_REG(DACOverlaySize, tmp);
106 tmp
147 u32 tmp; local
246 u32 tmp; local
290 u32 tmp; local
342 u32 tmp, ulStride; local
[all...]
/drivers/gpu/drm/radeon/
H A Dvce_v2_0.c36 u32 tmp; local
39 tmp = RREG32(VCE_CLOCK_GATING_B);
40 tmp |= 0xe70000;
41 WREG32(VCE_CLOCK_GATING_B, tmp);
43 tmp = RREG32(VCE_UENC_CLOCK_GATING);
44 tmp |= 0xff000000;
45 WREG32(VCE_UENC_CLOCK_GATING, tmp);
47 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
48 tmp &= ~0x3fc;
49 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
71 u32 orig, tmp; local
124 u32 tmp; local
[all...]
H A Drs400.c62 uint32_t tmp; local
67 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
68 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
110 uint32_t tmp; local
112 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
113 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
114 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
149 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
150 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
152 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
196 uint32_t tmp; local
236 uint32_t tmp; local
306 uint32_t tmp; local
[all...]
H A Dradeon_clocks.c195 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); local
198 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
200 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
388 uint32_t tmp; local
395 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
396 tmp &= ~RADEON_DONT_USE_XTALIN;
397 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
399 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
400 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
401 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
473 uint32_t tmp; local
[all...]
/drivers/staging/skein/
H A Dthreefish_block.c507 u64 tmp; local
513 tmp = b3 ^ b0;
514 b3 = (tmp >> 32) | (tmp << (64 - 32));
517 tmp = b1 ^ b2;
518 b1 = (tmp >> 32) | (tmp << (64 - 32));
521 tmp = b1 ^ b0;
522 b1 = (tmp >> 58) | (tmp << (6
2115 u64 tmp; local
5504 u64 tmp; local
[all...]
/drivers/staging/lustre/lustre/libcfs/
H A Dprng.c113 int rem, tmp; local
119 get_random_bytes(&tmp, sizeof(tmp));
120 tmp ^= cfs_rand();
121 memcpy(buf, &tmp, rem);
127 get_random_bytes(&tmp, sizeof(tmp));
128 *p = cfs_rand() ^ tmp;
134 get_random_bytes(&tmp, sizeof(tmp));
[all...]
/drivers/net/wireless/ti/wl18xx/
H A Dio.c29 u32 tmp; local
36 ret = wlcore_read32(wl, addr, &tmp);
40 tmp = (tmp & 0xffff0000) | val;
41 ret = wlcore_write32(wl, addr, tmp);
43 ret = wlcore_read32(wl, addr - 2, &tmp);
47 tmp = (tmp & 0xffff) | (val << 16);
48 ret = wlcore_write32(wl, addr - 2, tmp);
/drivers/video/fbdev/via/
H A Dvia_aux_vt1621.c37 u8 tmp; local
39 if (!via_aux_read(&drv, 0x1B, &tmp, 1) || tmp != 0x02)
H A Dvia_aux_ch7301.c37 u8 tmp; local
39 if (!via_aux_read(&drv, 0x4B, &tmp, 1) || tmp != 0x17)
H A Dvia_aux_vt1622.c37 u8 tmp; local
39 if (!via_aux_read(&drv, 0x1B, &tmp, 1) || tmp != 0x03)
H A Dvia_aux_vt1625.c37 u8 tmp; local
39 if (!via_aux_read(&drv, 0x1B, &tmp, 1) || tmp != 0x50)
H A Dvia_aux_vt1631.c39 u8 tmp[len]; local
41 if (!via_aux_read(&drv, 0x00, tmp, len) || memcmp(id, tmp, len))
H A Dvia_aux_vt1636.c39 u8 tmp[len]; local
41 if (!via_aux_read(&drv, 0x00, tmp, len) || memcmp(id, tmp, len))
/drivers/scsi/mvsas/
H A Dmv_64xx.c47 u32 tmp; local
49 tmp = mr32(MVS_PCS);
51 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT);
53 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
54 mw32(MVS_PCS, tmp);
86 u32 reg, tmp; local
97 tmp = reg;
99 tmp |= (1U << phy_id) << PCTL_LINK_OFFS;
101 tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS;
105 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
122 u32 tmp; local
142 u32 tmp; local
162 u32 tmp; local
212 u32 tmp; local
234 u32 tmp; local
257 u32 tmp, cctl; local
438 u32 tmp; local
447 u32 tmp; local
484 u32 tmp; local
499 u32 tmp; local
513 u32 tmp, offs; local
538 u32 tmp, offs; local
623 u32 tmp; local
640 u32 tmp; local
660 u32 tmp; local
756 u32 tmp = 0; local
[all...]
H A Dmv_94xx.c54 u32 tmp, setting_0 = 0, setting_1 = 0; local
97 tmp = mvs_read_port_vsr_data(mvi, phy_id);
98 tmp &= ~(0xFBE << 16);
99 tmp |= (((phy_tuning.trans_emp_en << 11) |
102 mvs_write_port_vsr_data(mvi, phy_id, tmp);
106 tmp = mvs_read_port_vsr_data(mvi, phy_id);
107 tmp &= ~(0xC000);
108 tmp |= (phy_tuning.trans_amp_adj << 14);
109 mvs_write_port_vsr_data(mvi, phy_id, tmp);
116 u32 tmp; local
263 u32 tmp; local
272 u32 tmp; local
304 u32 tmp; local
312 u32 tmp; local
337 u32 tmp, cctl; local
564 u32 tmp; local
579 u32 tmp; local
622 u32 tmp; local
638 u32 tmp; local
671 u32 tmp; local
866 u32 tmp; local
881 u32 tmp; local
988 u32 tmp = 0; local
[all...]
/drivers/devfreq/exynos/
H A Dexynos4_bus.c294 unsigned int tmp; local
304 tmp = data->dmc_divtable[index];
306 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
309 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
310 } while (tmp & 0x11111111);
313 tmp = data->top_divtable[index];
315 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
318 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
319 } while (tmp & 0x11111);
322 tmp
360 unsigned int tmp; local
525 int err = 0, tmp; local
664 u32 tmp; local
772 unsigned int tmp; local
[all...]
/drivers/gpu/drm/
H A Ddrm_rect.c76 int64_t tmp = src->x1 + (int64_t) diff * hscale; local
77 src->x1 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX);
81 int64_t tmp = src->y1 + (int64_t) diff * vscale; local
82 src->y1 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX);
86 int64_t tmp = src->x2 - (int64_t) diff * hscale; local
87 src->x2 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX);
91 int64_t tmp = src->y2 - (int64_t) diff * vscale; local
92 src->y2 = clamp_t(int64_t, tmp, INT_MIN, INT_MAX);
317 struct drm_rect tmp; local
320 tmp
391 struct drm_rect tmp; local
[all...]
/drivers/cpufreq/
H A Dexynos4210-cpufreq.c60 unsigned int tmp; local
64 tmp = apll_freq_4210[div_index].clk_div_cpu0;
66 __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
69 tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU);
70 } while (tmp & 0x1111111);
74 tmp = apll_freq_4210[div_index].clk_div_cpu1;
76 __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
79 tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
80 } while (tmp & 0x11);
85 unsigned int tmp, fre local
[all...]
/drivers/staging/comedi/drivers/addi-data/
H A Daddi_eeprom.c89 unsigned int tmp; local
100 tmp = inl(iobase);
104 if (tmp & EE93C76_DIN_BIT)
128 unsigned char tmp; local
148 tmp = inb(iobase + AMCC_OP_REG_MCSR_NVDATA);
152 val |= tmp;
154 val |= (tmp << 8);
185 unsigned short tmp; local
188 tmp = addi_eeprom_readw(iobase, type, addr + 6);
189 devpriv->s_EeParameters.i_NbrDiChannel = tmp;
206 unsigned short tmp; local
265 unsigned short tmp; local
285 unsigned short tmp; local
[all...]
/drivers/isdn/hardware/eicon/
H A Distream.c79 char tmp[4]; local
88 (dword *)&tmp[0],
90 if (tmp[0] & DIVA_DFIFO_READY) { /* No free blocks more */
109 tmp[1] = (char)to_write;
110 tmp[0] = (tmp[0] & DIVA_DFIFO_WRAP) |
113 if (tmp[0] & DIVA_DFIFO_LAST) {
114 tmp[2] = usr1;
115 tmp[3] = usr2;
123 (dword *)&tmp[
157 char tmp[4]; local
[all...]
/drivers/staging/olpc_dcon/
H A Dolpc_dcon_xo_1_5.c52 u_int8_t tmp; local
55 tmp = inb(VX855_GPI_STATUS_CHG);
56 return !!(tmp & BIT_GPIO12);
88 unsigned char tmp; local
93 tmp = inb(0x3c5);
96 tmp |= 0x20;
98 tmp &= ~0x20;
101 tmp |= 0x10;
103 tmp &= ~0x10;
105 tmp |
[all...]
/drivers/usb/musb/
H A Dmusb_io.h65 u16 tmp; local
68 tmp = __raw_readw(addr + (offset & ~1));
70 val = (tmp >> 8);
72 val = tmp & 0xff;
79 u16 tmp; local
81 tmp = __raw_readw(addr + (offset & ~1));
83 tmp = (data << 8) | (tmp & 0xff);
85 tmp = (tmp
[all...]
/drivers/video/fbdev/aty/
H A Dradeon_pm.c131 u32 tmp; local
136 tmp = INPLL(pllSCLK_CNTL);
137 tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK;
138 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK;
139 OUTPLL(pllSCLK_CNTL, tmp);
141 tmp = INPLL(pllMCLK_CNTL);
142 tmp |= (MCLK_CNTL__FORCE_MCLKA |
148 OUTPLL(pllMCLK_CNTL, tmp);
153 tmp = INPLL(pllSCLK_CNTL);
154 tmp |
332 u32 tmp; local
833 u32 tmp; local
1434 u32 tmp, tmp2; local
1459 u32 tmp; local
1473 u32 tmp; local
1580 u32 r2ec, tmp; local
1635 u32 tmp; local
1722 u32 tmp, i; local
1976 u32 tmp, i; local
2538 u32 tmp; local
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