/drivers/ata/ |
H A D | ahci_xgene.c | 196 static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel) argument 201 dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n", 202 mmio, channel); 204 val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
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H A D | libata-scsi.c | 2816 if (unlikely(scsidev->channel || scsidev->lun)) 2822 devno = scsidev->channel; 3401 scsidev->channel, scsidev->id, scsidev->lun, 3684 int channel = 0, id = 0; local 3692 channel = link->pmp; 3694 sdev = __scsi_add_device(ap->scsi_host, channel, id, 0, 3934 * @channel: Channel to scan 3947 int ata_scsi_user_scan(struct Scsi_Host *shost, unsigned int channel, argument 3961 if (channel != SCAN_WILD_CARD && channel) [all...] |
H A D | pata_bf54x.c | 793 * @ap: ATA channel to manipulate 840 unsigned int channel; local 847 channel = CH_ATAPI_TX; 850 channel = CH_ATAPI_RX; 874 set_dma_curr_desc_addr(channel, (unsigned long *)ap->bmdma_prd_dma); 875 set_dma_x_count(channel, 0); 876 set_dma_x_modify(channel, 0); 877 set_dma_config(channel, config); 959 * @ap: ATA channel to examine
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H A D | pata_ep93xx.c | 658 * to request only one channel, and reprogram it's direction at 679 /* Configure receive channel direction and source address */ 685 dev_err(&pdev->dev, "failed to configure rx dma channel\n"); 690 /* Configure transmit channel direction and destination address */ 696 dev_err(&pdev->dev, "failed to configure tx dma channel\n"); 708 struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE local 711 txd = dmaengine_prep_slave_sg(channel, qc->sg, qc->n_elem, qc->dma_dir, 724 dma_async_issue_pending(channel);
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H A D | pata_it821x.c | 59 * flaw that it has a single set of PIO/MWDMA timings per channel so 61 * single clock source per channel so mixed UDMA100/133 performance 121 * Program the PIO/MWDMA timing for this channel according to the 130 int channel = ap->port_no; local 138 pci_write_config_byte(pdev, 0x54 + 4 * channel, conf); 158 int channel = ap->port_no; local 168 pci_write_config_byte(pdev, 0x56 + 4 * channel + unit, conf); 171 pci_write_config_byte(pdev, 0x56 + 4 * channel, conf); 172 pci_write_config_byte(pdev, 0x56 + 4 * channel + 1, conf); 294 int channel local [all...] |
/drivers/atm/ |
H A D | horizon.c | 226 CBR. Each TX channel has a bucket (containing up to 31 cell units) 238 1. TX (TX channel setup and TX transfer) 246 Apart from a minor optimisation to not re-select the last channel, 252 If no TX channel is set up for this VC we wait for an idle one (if 255 At this point we have a TX channel ready for use. We wait for enough 268 TX close gets the TX lock and clears the channel from the "cache". 423 static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) { argument 424 wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel); 434 static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) { argument 435 wr_regw (dev, RX_CHANNEL_PORT_OFF, channel); 516 channel_to_vpivci(const u16 channel, short * vpi, int * vci) argument 526 vpivci_to_channel(u16 * channel, const short vpi, const int vci) argument 734 hrz_open_rx(hrz_dev * dev, u16 channel) argument 1507 u16 channel = vcc->channel; local 1591 u16 channel = vcc->channel; local 2134 u16 channel; local 2519 u16 channel = vcc->channel; local [all...] |
H A D | horizon.h | 190 /* TX channel config command port */ 202 /* TX channel config data port */ 255 /* RX channel port */ 274 /* Buffer pointers and channel types */ 293 /* Transmit channel stuff */ 295 /* Receive channel stuff */ 396 u16 channel; member in struct:__anon140 414 unsigned int rx_channel; // channel that the skb is going out on
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/drivers/char/ipmi/ |
H A D | ipmi_msghandler.c | 430 * tell which channel we are scanning. 638 if (addr1->channel != addr2->channel) 681 if (addr->channel != IPMI_BMC_CHANNEL) 686 if ((addr->channel == IPMI_BMC_CHANNEL) 687 || (addr->channel >= IPMI_MAX_CHANNELS) 688 || (addr->channel < 0)) 809 short channel, 825 if ((msg->addr.channel == channel) 807 intf_find_seq(ipmi_smi_t intf, unsigned char seq, short channel, unsigned char cmd, unsigned char netfn, struct ipmi_addr *addr, struct ipmi_recv_msg **recv_msg) argument 1113 ipmi_set_my_address(ipmi_user_t user, unsigned int channel, unsigned char address) argument 1124 ipmi_get_my_address(ipmi_user_t user, unsigned int channel, unsigned char *address) argument 1135 ipmi_set_my_LUN(ipmi_user_t user, unsigned int channel, unsigned char LUN) argument 1146 ipmi_get_my_LUN(ipmi_user_t user, unsigned int channel, unsigned char *address) argument [all...] |
/drivers/char/pcmcia/ |
H A D | synclink_cs.c | 239 #define CHA 0x00 /* channel A offset */ 240 #define CHB 0x40 /* channel B offset */ 336 static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask) argument 338 if (channel == CHA) { 346 static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask) argument 348 if (channel == CHA) { 686 static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel) argument 690 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) { 698 static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd) argument 700 wait_command_complete(info, channel); 2904 mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate) argument [all...] |
/drivers/char/xillybus/ |
H A D | xillybus_core.c | 116 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", 134 struct xilly_channel *channel; local 194 channel = ep->channels[msg_channel]; 196 if (msg_dir) { /* Write channel */ 197 if (msg_bufno >= channel->num_wr_buffers) { 201 spin_lock(&channel->wr_spinlock); 202 channel->wr_buffers[msg_bufno]->end_offset = 204 channel->wr_fpga_buf_idx = msg_bufno; 205 channel->wr_empty = 0; 206 channel 411 struct xilly_channel *channel; local 610 struct xilly_channel *channel; local 675 struct xilly_channel *channel = filp->private_data; local 993 xillybus_myflush(struct xilly_channel *channel, long timeout) argument 1169 struct xilly_channel *channel = container_of( local 1188 struct xilly_channel *channel = filp->private_data; local 1414 struct xilly_channel *channel; local 1563 struct xilly_channel *channel = filp->private_data; local 1663 struct xilly_channel *channel = filp->private_data; local 1737 struct xilly_channel *channel = filp->private_data; local [all...] |
/drivers/clk/versatile/ |
H A D | clk-sp810.c | 30 int channel; member in struct:clk_sp810_timerclken 48 return !!(val & (1 << SCCTRL_TIMERENnSEL_SHIFT(timerclken->channel))); 55 u32 val, shift = SCCTRL_TIMERENnSEL_SHIFT(timerclken->channel); 178 sp810->timerclken[i].channel = i;
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/drivers/clocksource/ |
H A D | samsung_pwm_timer.c | 48 * Each channel occupies 4 bits in TCON register, but there is a gap of 4 49 * bits (one channel) after channel 0, so channels have different numbering 52 * In addition, the location of autoreload bit for channel 4 (TCON channel 5) 85 static void samsung_timer_set_prescale(unsigned int channel, u16 prescale) argument 91 if (channel >= 2) 104 static void samsung_timer_set_divisor(unsigned int channel, u8 divisor) argument 106 u8 shift = TCFG1_SHIFT(channel); 123 static void samsung_time_stop(unsigned int channel) argument 140 samsung_time_setup(unsigned int channel, unsigned long tcnt) argument 163 samsung_time_start(unsigned int channel, bool periodic) argument 389 int channel; local [all...] |
/drivers/crypto/ux500/cryp/ |
H A D | cryp_core.c | 525 struct dma_chan *channel = NULL; local 538 channel = ctx->device->dma.chan_mem2cryp; 540 ctx->device->dma.sg_src_len = dma_map_sg(channel->device->dev, 555 desc = dmaengine_prep_slave_sg(channel, 562 channel = ctx->device->dma.chan_cryp2mem; 564 ctx->device->dma.sg_dst_len = dma_map_sg(channel->device->dev, 579 desc = dmaengine_prep_slave_sg(channel, 597 dma_async_issue_pending(channel);
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/drivers/crypto/ux500/hash/ |
H A D | hash_core.c | 157 struct dma_chan *channel = NULL; local 168 channel = ctx->device->dma.chan_mem2hash; 170 ctx->device->dma.sg_len = dma_map_sg(channel->device->dev, 182 desc = dmaengine_prep_slave_sg(channel, 195 dma_async_issue_pending(channel);
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/drivers/dma/ |
H A D | coh901318.c | 69 /* Linked channel request field. RM must == 11 */ 187 * struct coh_dma_channel - dma channel base 188 * @name: ascii name of dma channel 189 * @number: channel id number 191 * @priority_high: prio of channel, 0 low otherwise high. 1356 tmp += sprintf(tmp, "channel %d\n", i); 1441 int channel = cohc->id; local 1446 COH901318_CX_CTRL_SPACING * channel); 1452 int channel = cohc->id; local 1457 COH901318_CX_CFG_SPACING*channel); 1465 int channel = cohc->id; local 1484 int channel = cohc->id; local 1698 int channel = cohc->id; local 1743 int channel = cohc->id; local 1813 int channel = cohc->id; local 2144 int channel = cohc->id; local [all...] |
H A D | dmatest.c | 30 module_param_string(channel, test_channel, sizeof(test_channel), 32 MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)"); 42 "Number of threads to start per channel (default: 1)"); 80 * @channel: bus ID of the channel to test 82 * @threads_per_chan: number of threads to start per channel 91 char channel[20]; member in struct:dmatest_params 208 if (params->channel[0] == '\0') 210 return strcmp(dma_chan_name(chan), params->channel) [all...] |
H A D | imx-dma.c | 151 unsigned int channel; member in struct:imxdma_channel 187 struct imxdma_channel channel[IMX_DMA_CHANNELS]; member in struct:imxdma_engine 300 DMA_DAR(imxdmac->channel)); 303 DMA_SAR(imxdmac->channel)); 305 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel)); 307 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, " 308 "size 0x%08x\n", __func__, imxdmac->channel, 309 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)), 310 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)), 311 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel))); 320 int channel = imxdmac->channel; local 351 int channel = imxdmac->channel; local 372 int channel = imxdmac->channel; local [all...] |
H A D | imx-sdma.c | 132 u32 command : 8; /* command mostlky used for channel 0 */ 159 * struct sdma_state_registers - SDMA context for a channel 185 * struct sdma_context_data - sdma context specific to a channel 187 * @channel_state: channel state bits 236 * struct sdma_channel - housekeeping for a SDMA channel 238 * @sdma pointer to the SDMA engine for this channel 239 * @channel the channel number, matches dmaengine chan_id + 1 250 unsigned int channel; member in struct:sdma_channel 319 struct sdma_channel channel[MAX_DMA_CHANNEL member in struct:sdma_engine 474 int channel = sdmac->channel; local 506 sdma_enable_channel(struct sdma_engine *sdma, int channel) argument 575 int channel = sdmac->channel; local 587 int channel = sdmac->channel; local 674 int channel = fls(stat) - 1; local 783 int channel = sdmac->channel; local 835 int channel = sdmac->channel; local 902 int channel = sdmac->channel; local 917 int channel = sdmac->channel; local 1032 int channel = sdmac->channel; local 1133 int channel = sdmac->channel; local [all...] |
H A D | omap-dma.c | 294 /* Enable channel */ 456 * this point, and freeing them when our virtual channel becomes idle. 483 unsigned status, channel; local 494 while ((channel = ffs(status)) != 0) { 498 channel -= 1; 499 mask = BIT(channel); 502 c = od->lch_map[channel]; 505 dev_err(od->ddev.dev, "invalid channel %u\n", channel); 512 omap_dma_callback(channel, cs [all...] |
/drivers/dma/ipu/ |
H A D | ipu_idmac.c | 116 static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel) argument 120 switch (channel) { 135 static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel) argument 139 switch (channel) { 153 static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel) argument 158 switch (channel) { 563 static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel, argument 569 reg |= 1UL << channel; 571 reg &= ~(1UL << channel); 578 static uint32_t ipu_channel_conf_mask(enum ipu_channel channel) argument 608 enum ipu_channel channel = ichan->dma_chan.chan_id; local 660 enum ipu_channel channel = ichan->dma_chan.chan_id; local 713 ipu_select_buffer(enum ipu_channel channel, int buffer_n) argument 735 enum ipu_channel channel = ichan->dma_chan.chan_id; local 954 enum ipu_channel channel = ichan->dma_chan.chan_id; local 1011 enum ipu_channel channel = ichan->dma_chan.chan_id; local 1074 enum ipu_channel channel = ichan->dma_chan.chan_id; local [all...] |
H A D | ipu_intern.h | 163 struct idmac_channel channel[IPU_CHANNELS_NUM]; member in struct:ipu
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/drivers/dma/sh/ |
H A D | rcar-hpbdma.c | 31 /* DMA channel registers */ 97 char dev_id[16]; /* unique name per DMAC of channel */ 338 * outstanding DMA transfer per channel, and by the time 405 const struct hpb_dmae_channel *channel = pdata->channels; local 409 for (i = 0; i < pdata->num_channels; i++, channel++) { 410 if (channel->s_id == slave_id) { 419 dev_dbg(dev, " -- channel->ch_irq: %d\n", 420 channel->ch_irq); 425 err = shdma_request_irq(&hpb_chan->shdma_chan, channel->ch_irq, 429 "DMA channel request_ir [all...] |
/drivers/edac/ |
H A D | amd64_edac.c | 718 edac_dbg(1, " NB two channel DRAM capable: %s\n", 1011 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); 1012 if (err->channel < 0) { 1029 * channel number when using non-chipkill memory. This method 1033 err->channel = ((sys_addr & BIT(3)) != 0); 1143 amd64_info("MCT channel count: %d\n", channels); 1230 edac_dbg(0, " channel interleave: %s, " 1240 * Determine channel (DCT) based on the interleaving mode (see F15h M30h BKDG, 1247 u8 channel = 0; local 1255 channel 1473 u8 channel; local 1555 u8 channel, alias_channel, leg_mmio_hole, dct_sel, dct_offset_en; local [all...] |
H A D | amd64_edac.h | 395 int channel; member in struct:err_info
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H A D | cpc925_edac.c | 359 case 1: /* Single channel */ 362 case 2: /* Dual channel */ 539 int csrow = 0, channel = 0; local 556 channel = cpc925_mc_find_channel(mci, syndrome); 559 csrow, channel, -1, 914 /* Return 0 for single channel; 1 for dual channel */ 923 * Dual channel only when 128-bit wide physical bus 930 edac_dbg(0, "%s channel\n", (dual > 0) ? "Dual" : "Single");
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