/drivers/ata/ |
H A D | pata_mpc52xx.c | 448 unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE), si; local 452 if (read) 466 if (read) { 505 unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE); local 517 if (read) {
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/drivers/atm/ |
H A D | ambassador.h | 395 __be32 read; member in struct:__anon99::__anon100::__anon108
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H A D | fore200e.h | 732 u32 recv; /* read register */ 805 u32 (*read)(volatile u32 __iomem *); member in struct:fore200e_bus 912 #define PCA200E_HCR_RESET (1<<0) /* read / write */ 913 #define PCA200E_HCR_HOLD_LOCK (1<<1) /* read / write */ 914 #define PCA200E_HCR_I960FAIL (1<<2) /* read */ 916 #define PCA200E_HCR_HOLD_ACK (1<<3) /* read */ 918 #define PCA200E_HCR_OUTFULL (1<<4) /* read */ 920 #define PCA200E_HCR_ESPHOLD (1<<5) /* read */ 921 #define PCA200E_HCR_INFULL (1<<6) /* read */ 922 #define PCA200E_HCR_TESTMODE (1<<7) /* read */ [all...] |
H A D | iphase.h | 294 struct dle *read; member in struct:dle_q 669 ffreg_t prq_rd_ptr; /* Packet Ready Queue read pointer */ 673 ffreg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */ 697 ffreg_t vbrwq_rptr; /* VBR wait queue read pointer */ 699 ffreg_t abrwq_rptr; /* ABR wait queue read pointer */ 701 ffreg_t ubrwq_rptr; /* UBR wait queue read pointer */ 722 rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */ 723 rreg_t err_cntr; /* Error Counter (cleared on read) */ 727 rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */ 728 rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */ [all...] |
H A D | lanai.c | 105 * We normally read the onboard EEPROM in order to discover our MAC 396 Reset_Reg = 0x00, /* Reset; read for chip type; bits: */ 421 #define READMODE_PLAIN (0) /* Plain memory read */ 422 #define READMODE_LINE (2) /* Memory read line */ 423 #define READMODE_MULTIPLE (3) /* Memory read multiple */ 563 "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n", 779 int read, write, lastread = -1; local 799 read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)); 800 if (read == write && /* Is TX buffer empty? */ 805 if (read ! [all...] |
/drivers/base/ |
H A D | devcoredump.c | 34 /* if data isn't read by userspace after 5 minutes then delete it */ 42 ssize_t (*read)(char *buffer, loff_t offset, size_t count, member in struct:devcd_entry 90 return devcd->read(buffer, offset, count, devcd->data, devcd->datalen); 108 .read = devcd_data_read, 171 * dev_coredumpm - create device coredump with read/free methods 173 * @owner: the module that contains the read/free functions, use %THIS_MODULE 174 * @data: data cookie for the @read/@free functions 177 * @read: function to read from the given buffer 181 * been read ye [all...] |
/drivers/base/regmap/ |
H A D | internal.h | 154 int (*read)(struct regmap *map, unsigned int reg, unsigned int *value); member in struct:regcache_ops
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/drivers/block/ |
H A D | ps3disk.c | 126 const char *op = write ? "write" : "read"; 231 int res, read, error; local 260 read = 0; 263 read = !rq_data_dir(req); 264 op = read ? "read" : "write"; 274 if (read)
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/drivers/block/rsxx/ |
H A D | cregs.c | 285 "Buffer not given for read.\n"); 435 * This read is needed to verify that there has not been any 439 * for the timeout. This is a dummy read. 457 int read) 464 op = read ? CREG_OP_READ : CREG_OP_WRITE; 669 int read) 671 unsigned int op = read ? CREG_OP_READ : CREG_OP_WRITE; 679 int read) 691 st = issue_reg_cmd(card, &cmd, read); 699 if (read) { 452 issue_creg_rw(struct rsxx_cardinfo *card, u32 addr, unsigned int size8, void *data, int stream, int read) argument 667 issue_reg_cmd(struct rsxx_cardinfo *card, struct rsxx_reg_access *cmd, int read) argument 677 rsxx_reg_access(struct rsxx_cardinfo *card, struct rsxx_reg_access __user *ucmd, int read) argument [all...] |
/drivers/char/ |
H A D | mem.c | 102 ssize_t read, sz; local 110 read = 0; 121 read += sz; 151 read += sz; 154 *ppos += read; 155 return read; 379 ssize_t low_count, read, sz; local 383 read = 0; 397 read += sz; 416 read [all...] |
/drivers/clk/ |
H A D | clk-axi-clkgen.c | 61 int (*read)(struct axi_clkgen *axi_clkgen, unsigned int reg, member in struct:axi_clkgen_mmcm_ops 86 return axi_clkgen->mmcm_ops->read(axi_clkgen, reg, val); 271 .read = axi_clkgen_v1_mmcm_read, 349 .read = axi_clkgen_v2_mmcm_read,
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/drivers/edac/ |
H A D | i7core_edac.c | 415 /* MC_MAX_DOD read functions */ 880 u32 read; local 891 pci_read_config_dword(dev, where, &read); 893 if (read == val) 900 where, val, read); 1041 edac_dbg(0, "Inject error read: 0x%018x\n", injectmask); 1737 optype = "read error"; 1755 err = "read ECC error"; 1987 /* Set speed if a valid speed is read */
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H A D | ppc4xx_edac.c | 97 * the bus master and the transaction direction (i.e. read or write) 237 * mfsdram - read and return controller register data 239 * @idcr_n: The indirect DCR register to read. 244 * Returns the read data. 563 bool read; local 571 read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ); 577 (read ? "Read" : "Write"), 663 * While we read all of them, for correctable errors, we only expect
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/drivers/gpio/ |
H A D | gpio-lp3943.c | 95 u8 addr, read; local 110 err = lp3943_read_byte(lp3943_gpio->lp3943, addr, &read); 114 return !!(read & BIT(offset)); 122 u8 read; local 125 err = lp3943_read_byte(lp3943, mux[offset].reg, &read); 129 read = (read & mux[offset].mask) >> mux[offset].shift; 131 if (read == LP3943_GPIO_OUT_HIGH) 133 else if (read == LP3943_GPIO_OUT_LOW)
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H A D | gpio-mcp23s08.c | 60 int (*read)(struct mcp23s08 *mcp, unsigned reg); member in struct:mcp23s08_ops 152 .read = mcp23008_read, 158 .read = mcp23017_read, 254 .read = mcp23s08_read, 260 .read = mcp23s17_read, 289 status = mcp->ops->read(mcp, MCP_GPIO); 347 intf = mcp->ops->read(mcp, MCP_INTF); 355 intcap = mcp->ops->read(mcp, MCP_INTCAP); 647 status = mcp->ops->read(mcp, MCP_IOCON);
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H A D | gpio-pcf857x.c | 76 * The pcf857x, pca857x, and pca967x chips only expose one read and one 79 * a bit like one. This is described as "quasi-bidirectional"; read the 98 int (*read)(struct i2c_client *client); member in struct:pcf857x 157 value = gpio->read(gpio->client); 202 status = gpio->read(gpio->client); 339 gpio->read = i2c_read_le8; 357 gpio->read = i2c_read_le16; 383 * came out of reset (if any). We can't read the latched output.
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/drivers/gpu/drm/i915/ |
H A D | intel_uncore.c | 59 /* w/a for a sporadic read returning 0 by waiting for the GT 162 * So, we need to read the FREE_ENTRIES everytime */ 399 * Generally this is called implicitly by the register read function. However, 517 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read, argument 520 const char *op = read ? "reading" : "writing to"; 852 * ECOBUS read will return zero. Which will be 1156 * the read
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/drivers/gpu/drm/nouveau/core/engine/perfmon/ |
H A D | priv.h | 62 void (*read)(struct nouveau_perfmon *, struct nouveau_perfdom *, member in struct:nouveau_funcdom
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/drivers/gpu/drm/nouveau/core/include/subdev/ |
H A D | clock.h | 90 int (*read)(struct nouveau_clock *, enum nv_clk_src); member in struct:nouveau_clock
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H A D | timer.h | 37 u64 (*read)(struct nouveau_timer *); member in struct:nouveau_timer
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/drivers/gpu/drm/nouveau/ |
H A D | nouveau_fence.h | 41 u32 (*read)(struct nouveau_channel *); member in struct:nouveau_fence_chan
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/drivers/hv/ |
H A D | ring_buffer.c | 41 u32 read; local 52 hv_get_ringbuffer_availbytes(rbi, &read, &write); 54 return read; 67 * the ring buffer before exiting the read loop. Further, 166 * Get the next read location for the specified ring buffer 179 * Get the next read location + offset for the specified ring buffer. 198 * Set the next read location for the specified ring buffer 238 * Get the read and write indices as u64 of the specified ring buffer 422 /* is empty since the read index == write index */ 466 * Read without advancing the read inde [all...] |
/drivers/i2c/busses/ |
H A D | i2c-pasemi.c | 71 dev_dbg(&smbus->dev->dev, "smbus read reg %lx val %08x\n", 119 int read, i, err; local 122 read = msg->flags & I2C_M_RD ? 1 : 0; 124 TXFIFO_WR(smbus, MTXFIFO_START | (msg->addr << 1) | read); 126 if (read) {
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H A D | i2c-powermac.c | 46 int read = (read_write == I2C_SMBUS_READ); local 47 int addrdir = (addr << 1) | read; 58 mode = read ? pmac_i2c_mode_combined : pmac_i2c_mode_stdsub; 74 if (!read) { 132 if (size == I2C_SMBUS_WORD_DATA && read) { 153 int read; local 164 read = (msgs->flags & I2C_M_RD) != 0; 165 addrdir = (msgs->addr << 1) | read; 182 addrdir & 1 ? "read from" : "write to", 186 addrdir & 1 ? "read fro [all...] |
H A D | i2c-rcar.c | 250 int read = !!rcar_i2c_is_recv(priv); local 252 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read); 255 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
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