/drivers/char/xilinx_hwicap/ |
H A D | fifo_icap.c | 359 u32 reg_data; local 364 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); 367 reg_data | XHI_CR_SW_RESET_MASK); 370 reg_data & (~XHI_CR_SW_RESET_MASK)); 380 u32 reg_data; local 385 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); 388 reg_data | XHI_CR_FIFO_CLR_MASK); 391 reg_data & (~XHI_CR_FIFO_CLR_MASK));
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H A D | xilinx_hwicap.c | 256 * @reg_data: returns the value of the register. 262 u32 reg, u32 *reg_data) 308 status = drvdata->config->get_configuration(drvdata, reg_data, 1); 261 hwicap_get_configuration_register(struct hwicap_drvdata *drvdata, u32 reg, u32 *reg_data) argument
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/drivers/clk/rockchip/ |
H A D | clk-cpu.c | 51 * @reg_data: cpu-specific register settings 65 const struct rockchip_cpuclk_reg_data *reg_data; member in struct:rockchip_cpuclk 92 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; local 93 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); 95 clksel0 >>= reg_data->div_core_shift; 96 clksel0 &= reg_data->div_core_mask; 125 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; local 141 if (alt_div > reg_data 174 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; local 231 rockchip_clk_register_cpuclk(const char *name, const char **parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates, void __iomem *reg_base, spinlock_t *lock) argument [all...] |
H A D | clk.c | 302 const struct rockchip_cpuclk_reg_data *reg_data, 309 reg_data, rates, nrates, reg_base, 299 rockchip_clk_register_armclk(unsigned int lookup_id, const char *name, const char **parent_names, u8 num_parents, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates) argument
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/drivers/extcon/ |
H A D | extcon-rt8973a.c | 35 struct reg_data { struct 59 struct reg_data *reg_data; member in struct:rt8973a_muic_info 75 static struct reg_data rt8973a_reg_data[] = { 546 u8 reg = info->reg_data[i].reg; 547 u8 mask = info->reg_data[i].mask; 550 if (info->reg_data[i].invert) 551 val = ~info->reg_data[i].val; 553 val = info->reg_data[i].val; 596 info->reg_data [all...] |
H A D | extcon-sm5502.c | 34 struct reg_data { struct 55 struct reg_data *reg_data; member in struct:sm5502_muic_info 70 static struct reg_data sm5502_reg_data[] = { 523 unsigned int reg_data, vendor_id, version_id; local 527 ret = regmap_read(info->regmap, SM5502_REG_DEVICE_ID, ®_data); 534 vendor_id = ((reg_data & SM5502_REG_DEVICE_ID_VENDOR_MASK) >> 536 version_id = ((reg_data & SM5502_REG_DEVICE_ID_VERSION_MASK) >> 546 if (!info->reg_data[i].invert) 547 val |= ~info->reg_data[ [all...] |
/drivers/gpio/ |
H A D | gpio-sx150x.c | 35 u8 reg_data; member in struct:sx150x_device_data 67 .reg_data = 0x08, 82 .reg_data = 0x11, 177 u8 reg = chip->dev_cfg->reg_data; 203 chip->dev_cfg->reg_data, 223 chip->dev_cfg->reg_data,
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/drivers/gpu/drm/radeon/ |
H A D | radeon_atombios.c | 3964 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = local 3985 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 3987 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 3991 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 3996 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 4005 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4006 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 4008 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
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/drivers/media/dvb-frontends/ |
H A D | drxk_hard.c | 2493 u16 reg_data = 0; local 2522 ®_data); 2526 eq_reg_td_sqr_err_i = (u32) reg_data; 2531 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data); 2535 eq_reg_td_sqr_err_q = (u32) reg_data;
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H A D | stv0900_core.c | 133 u8 reg_data) 146 data[2] = reg_data; 132 stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr, u8 reg_data) argument
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/drivers/media/tuners/ |
H A D | xc5000.c | 497 u16 reg_data; local 500 result = xc5000_readreg(priv, XREG_FREQ_ERROR, ®_data); 504 tmp = (u32)reg_data; 540 u16 reg_data; local 543 result = xc5000_readreg(priv, XREG_HSYNC_FREQ, ®_data); 547 (*hsync_freq_hz) = ((reg_data & 0x0fff) * 763)/100;
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/drivers/media/usb/gspca/m5602/ |
H A D | m5602_s5k83a.c | 45 static int s5k83a_get_rotation(struct sd *sd, u8 *reg_data); 407 static int s5k83a_get_rotation(struct sd *sd, u8 *reg_data) argument 409 int err = m5602_read_bridge(sd, M5602_XB_GPIO_DAT, reg_data); 410 *reg_data = (*reg_data & S5K83A_GPIO_ROTATION_MASK) ? 0 : 1;
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/drivers/mfd/ |
H A D | max14577.c | 276 u8 reg_data, vendor_id, device_id; local 280 ®_data); 287 vendor_id = ((reg_data & DEVID_VENDORID_MASK) >> 289 device_id = ((reg_data & DEVID_DEVICEID_MASK) >>
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H A D | max77693.c | 154 unsigned int reg_data; local 177 ®_data); 182 dev_info(max77693->dev, "device ID: 0x%x\n", reg_data);
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/drivers/net/ethernet/atheros/atl1c/ |
H A D | atl1c_main.c | 1589 u32 reg_data; local 1592 AT_READ_REG(hw, REG_ISR, ®_data); 1593 status = reg_data & hw->intr_mask;
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/drivers/net/ethernet/intel/e1000e/ |
H A D | 80003es2lan.c | 744 u32 reg_data; local 782 reg_data = er32(TXDCTL(0)); 783 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 785 ew32(TXDCTL(0), reg_data); 788 reg_data = er32(TXDCTL(1)); 789 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 791 ew32(TXDCTL(1), reg_data); 794 reg_data 1032 u16 reg_data; local 1119 u16 reg_data, reg_data2; local 1164 u16 reg_data, reg_data2; local [all...] |
H A D | 82571.c | 1085 u32 reg_data; local 1119 reg_data = er32(TXDCTL(0)); 1120 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 1122 ew32(TXDCTL(0), reg_data); 1131 reg_data = er32(GCR); 1132 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1133 ew32(GCR, reg_data); 1136 reg_data = er32(TXDCTL(1)); 1137 reg_data [all...] |
H A D | ich8lan.c | 1910 u16 word_addr, reg_data, reg_addr, phy_page = 0; local 1988 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 1999 phy_page = reg_data; 2006 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 4263 u16 reg_data; local 4278 ®_data); 4281 reg_data |= 0x3F; 4283 reg_data); 4306 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 4310 reg_data 4539 u16 reg_data; local [all...] |
/drivers/net/ethernet/intel/igb/ |
H A D | igb_main.c | 1745 u32 reg_data = rd32(E1000_CTRL_EXT); local 1747 reg_data |= E1000_CTRL_EXT_PFRSTD; 1748 wr32(E1000_CTRL_EXT, reg_data); 3087 u32 reg_data = rd32(E1000_CTRL_EXT); local 3089 reg_data |= E1000_CTRL_EXT_PFRSTD; 3090 wr32(E1000_CTRL_EXT, reg_data);
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/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_ethtool.c | 1665 u32 rctl, reg_data; local 1683 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1684 reg_data |= IXGBE_DMATXCTL_TE; 1685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1724 u32 reg_data; local 1728 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1729 reg_data |= IXGBE_HLREG0_LPBK; 1730 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1732 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1733 reg_data | 1778 u32 reg_data; local [all...] |
/drivers/net/ethernet/marvell/ |
H A D | mvpp2.c | 4031 u32 reg_data; local 4037 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 4039 if (reg_data != 0) 4041 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 4049 reg_data); 4058 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 4059 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
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H A D | pxa168_eth.c | 310 unsigned int reg_data; local 312 reg_data = rdl(pep, PHY_ADDRESS); 314 return (reg_data >> (5 * pep->port_num)) & 0x1f; 319 u32 reg_data; local 322 reg_data = rdl(pep, PHY_ADDRESS); 323 reg_data &= ~(0x1f << addr_shift); 324 reg_data |= (phy_addr & 0x1f) << addr_shift; 325 wrl(pep, PHY_ADDRESS, reg_data);
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/drivers/net/ethernet/micrel/ |
H A D | ks8851_mll.c | 642 u16 reg_data = 0; local 645 reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF; 646 reg_data |= ks_rdreg8(ks, KS_CCR+1) << 8; 649 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED; 655 if (reg_data & CCR_8BIT) { 658 } else if (reg_data & CCR_16BIT) {
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/drivers/net/ethernet/xilinx/ |
H A D | xilinx_emaclite.c | 158 u32 reg_data; local 161 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET); 162 __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK, 181 u32 reg_data; local 187 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET); 188 __raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), 192 reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET); 193 __raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), 315 u32 reg_data; local 326 reg_data 378 u32 reg_data; local 461 u32 reg_data; local [all...] |
/drivers/net/wireless/ath/wcn36xx/ |
H A D | dxe.c | 47 #define wcn36xx_dxe_write_register_x(wcn, reg, reg_data) \ 50 wcn36xx_dxe_write_register(wcn, reg ## _3680, reg_data); \ 52 wcn36xx_dxe_write_register(wcn, reg ## _3660, reg_data); \ 258 int reg_data = 0; local 262 ®_data); 264 reg_data |= wcn_ch; 268 (int)reg_data); 684 int reg_data = 0, ret; local 686 reg_data = WCN36XX_DXE_REG_RESET; 687 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data); [all...] |