Searched refs:io_base (Results 1 - 25 of 72) sorted by path

123

/drivers/ata/
H A Dpata_hpt37x.c707 unsigned long io_base = pci_resource_start(pdev, 4); local
716 io_base = pci_resource_start(pdev_0, 4);
717 freq = inl(io_base + 0x90);
720 freq = inl(io_base + 0x90);
H A Dpata_pcmcia.c204 unsigned long io_base, ctl_base; local
224 io_base = pdev->resource[0]->start;
239 io_addr = devm_ioport_map(&pdev->dev, io_base, 8);
276 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io_base, ctl_base);
/drivers/char/hw_random/
H A Dtimeriomem-rng.c37 void __iomem *io_base; member in struct:timeriomem_rng_private_data
72 *data = readl(priv->io_base);
161 priv->io_base = devm_ioremap_resource(&pdev->dev, res);
162 if (IS_ERR(priv->io_base)) {
163 err = PTR_ERR(priv->io_base);
174 priv->io_base, period);
/drivers/char/pcmcia/
H A Dsynclink_cs.c201 unsigned int io_base; /* base I/O address of adapter */ member in struct:_mgslpc_info
321 #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
322 #define read_reg(info, reg) inb((info)->io_base + (reg))
324 #define read_reg16(info, reg) inw((info)->io_base + (reg))
325 #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
600 info->io_base = link->resource[0]->start;
2566 info->device_name, info->io_base, info->irq_level);
2746 info->device_name, info->io_base, info->irq_level);
3818 __FILE__, __LINE__, info->device_name, (unsigned short)(info->io_base));
4301 dev->base_addr = info->io_base;
[all...]
/drivers/crypto/
H A Datmel-aes.c103 void __iomem *io_base; member in struct:atmel_aes_dev
217 return readl_relaxed(dd->io_base + offset);
223 writel_relaxed(value, dd->io_base + offset);
1382 aes_dd->io_base = ioremap(aes_dd->phys_base, aes_phys_size);
1383 if (!aes_dd->io_base) {
1423 iounmap(aes_dd->io_base);
1458 iounmap(aes_dd->io_base);
H A Datmel-sha.c124 void __iomem *io_base; member in struct:atmel_sha_dev
153 return readl_relaxed(dd->io_base + offset);
159 writel_relaxed(value, dd->io_base + offset);
1431 sha_dd->io_base = ioremap(sha_dd->phys_base, sha_phys_size);
1432 if (!sha_dd->io_base) {
1486 iounmap(sha_dd->io_base);
1517 iounmap(sha_dd->io_base);
H A Datmel-tdes.c96 void __iomem *io_base; member in struct:atmel_tdes_dev
183 return readl_relaxed(dd->io_base + offset);
189 writel_relaxed(value, dd->io_base + offset);
1416 tdes_dd->io_base = ioremap(tdes_dd->phys_base, tdes_phys_size);
1417 if (!tdes_dd->io_base) {
1476 iounmap(tdes_dd->io_base);
1512 iounmap(tdes_dd->io_base);
H A Domap-aes.c148 void __iomem *io_base; member in struct:omap_aes_dev
198 _read_ret = __raw_readl(dd->io_base + offset); \
206 return __raw_readl(dd->io_base + offset);
215 __raw_writel(value, dd->io_base + offset); \
221 __raw_writel(value, dd->io_base + offset);
1184 dd->io_base = devm_ioremap_resource(dev, &res);
1185 if (IS_ERR(dd->io_base)) {
1186 err = PTR_ERR(dd->io_base);
H A Domap-des.c129 void __iomem *io_base; member in struct:omap_des_dev
179 _read_ret = __raw_readl(dd->io_base + offset); \
187 return __raw_readl(dd->io_base + offset);
196 __raw_writel(value, dd->io_base + offset); \
202 __raw_writel(value, dd->io_base + offset);
1084 dd->io_base = devm_ioremap_resource(dev, res);
1085 if (IS_ERR(dd->io_base)) {
1086 err = PTR_ERR(dd->io_base);
H A Domap-sham.c218 void __iomem *io_base; member in struct:omap_sham_dev
247 return __raw_readl(dd->io_base + offset);
253 __raw_writel(value, dd->io_base + offset);
1920 dd->io_base = devm_ioremap_resource(dev, &res);
1921 if (IS_ERR(dd->io_base)) {
1922 err = PTR_ERR(dd->io_base);
/drivers/gpu/drm/qxl/
H A Dqxl_cmd.c284 long addr = qdev->io_base + port;
360 outb(0, qdev->io_base + QXL_IO_NOTIFY_OOM);
365 outb(0, qdev->io_base + QXL_IO_FLUSH_RELEASE);
419 outb(0, qdev->io_base + QXL_IO_LOG);
424 outb(0, qdev->io_base + QXL_IO_RESET);
H A Dqxl_drv.h258 int io_base; member in struct:qxl_device
H A Dqxl_irq.c67 outb(0, qdev->io_base + QXL_IO_UPDATE_IRQ);
H A Dqxl_kms.c139 qdev->io_base = pci_resource_start(pdev, 3);
194 qdev->io_base + QXL_IO_NOTIFY_CMD,
202 qdev->io_base + QXL_IO_NOTIFY_CMD,
/drivers/hwspinlock/
H A Domap_hwspinlock.c87 void __iomem *io_base; local
97 io_base = ioremap(res->start, resource_size(res));
98 if (!io_base)
113 i = readl(io_base + SYSSTATUS_OFFSET);
141 hwlock->priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i;
154 iounmap(io_base);
161 void __iomem *io_base = bank->lock[0].priv - LOCK_BASE_OFFSET; local
171 iounmap(io_base);
H A Du8500_hsem.c100 void __iomem *io_base; local
111 io_base = ioremap(res->start, resource_size(res));
112 if (!io_base)
116 val = readl(io_base + HSEM_CTRL_REG);
117 writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG);
120 writel(0xFFFF, io_base + HSEM_ICRALL);
131 hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i;
147 iounmap(io_base);
154 void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET; local
158 writel(0xFFFF, io_base
[all...]
/drivers/i2c/busses/
H A Di2c-pca-platform.c36 unsigned long io_base; member in struct:i2c_pca_pf_data
169 i2c->io_base = res->start;
272 release_mem_region(i2c->io_base, i2c->io_size);
/drivers/ide/
H A Dhpt366.c911 unsigned long io_base = pci_resource_start(dev, 4); local
943 outb(0x0e, io_base + 0x9c);
970 unsigned long io_base = pci_resource_start(dev1, 4); local
972 temp = inl(io_base + 0x90);
975 temp = inl(io_base + 0x90);
1146 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
H A Dide-cs.c193 unsigned long io_base, ctl_base; local
207 io_base = link->resource[0]->start;
227 host = idecs_register(io_base, ctl_base, link->irq, link);
230 host = idecs_register(io_base + 0x10, ctl_base + 0x10,
/drivers/input/keyboard/
H A Dspear-keyboard.c57 void __iomem *io_base; member in struct:spear_kbd
76 sts = readl_relaxed(kbd->io_base + STATUS_REG);
86 val = readl_relaxed(kbd->io_base + DATA_REG) &
97 writel_relaxed(0, kbd->io_base + STATUS_REG);
121 writel_relaxed(val, kbd->io_base + MODE_CTL_REG);
122 writel_relaxed(1, kbd->io_base + STATUS_REG);
125 val = readl_relaxed(kbd->io_base + MODE_CTL_REG);
127 writel_relaxed(val, kbd->io_base + MODE_CTL_REG);
138 val = readl_relaxed(kbd->io_base + MODE_CTL_REG);
140 writel_relaxed(val, kbd->io_base
[all...]
/drivers/media/platform/s3c-camif/
H A Dcamif-core.c441 camif->io_base = devm_ioremap_resource(dev, mres);
442 if (IS_ERR(camif->io_base))
443 return PTR_ERR(camif->io_base);
H A Dcamif-core.h264 * @io_base: start address of the mmaped CAMIF registers
302 void __iomem *io_base; member in struct:camif_dev
H A Dcamif-regs.c16 #define camif_write(_camif, _off, _val) writel(_val, (_camif)->io_base + (_off))
17 #define camif_read(_camif, _off) readl((_camif)->io_base + (_off))
603 u32 cfg = readl(camif->io_base + registers[i].offset);
H A Dcamif-regs.h265 return readl(vp->camif->io_base + S3C_CAMIF_REG_CISTATUS(vp->id,
/drivers/mfd/
H A Dkempld-core.c461 pld->io_base = devm_ioport_map(dev, ioport->start,
463 if (!pld->io_base)
466 pld->io_index = pld->io_base;
467 pld->io_data = pld->io_base + 1;

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